☆92May 29, 2026Updated last month
Alternatives and similar repositories for testchipip
Users that are interested in testchipip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆248Apr 29, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated 10 months ago
- ☆385Jun 14, 2026Updated 2 weeks ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- A fault-injection framework using Chisel and FIRRTL☆38Sep 17, 2025Updated 9 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆64Jun 27, 2025Updated last year
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- A Scala library for Context-Dependent Environments☆50Apr 25, 2024Updated 2 years ago
- Open-source high-performance non-blocking cache☆99Jun 17, 2026Updated 2 weeks ago
- Open-source non-blocking L2 cache☆63Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A libgloss replacement for RISC-V that supports HTIF☆45May 3, 2024Updated 2 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆90Mar 17, 2026Updated 3 months ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆59Jun 22, 2026Updated last week
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Chisel examples and code snippets☆282Aug 1, 2022Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆165Jan 25, 2024Updated 2 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 9 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆615Aug 9, 2024Updated last year
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,299Jun 22, 2026Updated last week
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- Chisel Things for OFDM☆33Jul 1, 2020Updated 6 years ago
- A Chisel RTL generator for network-on-chip interconnects☆232Nov 7, 2025Updated 7 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- educational microarchitectures for risc-v isa☆749Sep 1, 2025Updated 10 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- ☆81Feb 27, 2024Updated 2 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆322Mar 6, 2026Updated 3 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆225Jan 11, 2026Updated 5 months ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago