ucb-bar / testchipipLinks
☆84Updated last week
Alternatives and similar repositories for testchipip
Users that are interested in testchipip are comparing it to the libraries listed below
Sorting:
- Provides various testers for chisel users☆100Updated 2 years ago
- Chisel/Firrtl execution engine☆153Updated 10 months ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 4 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆236Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- ☆47Updated last month
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆82Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- Open source high performance IEEE-754 floating unit☆73Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- A Scala library for Context-Dependent Environments☆47Updated last year
- Open-source high-performance non-blocking cache☆83Updated 3 weeks ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- The multi-core cluster of a PULP system.☆101Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 10 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 3 months ago
- Generic Register Interface (contains various adapters)☆121Updated last week
- ☆81Updated last year
- Chisel components for FPGA projects☆124Updated last year
- Simple runtime for Pulp platforms☆48Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 7 months ago
- RISC-V Torture Test☆196Updated 11 months ago
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- OmniXtend cache coherence protocol☆82Updated last week
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year