seldridge / rocket-rocc-examplesLinks
Tests for example Rocket Custom Coprocessors
☆75Updated 5 years ago
Alternatives and similar repositories for rocket-rocc-examples
Users that are interested in rocket-rocc-examples are comparing it to the libraries listed below
Sorting:
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- Public release☆58Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Updated 3 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- An integrated CGRA design framework☆91Updated 10 months ago
- ☆82Updated last year
- Chisel components for FPGA projects☆128Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- ☆87Updated last year
- Chisel Learning Journey☆111Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- An open-source UCIe implementation☆82Updated 2 weeks ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆58Updated 6 years ago
- ☆109Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆77Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆17Updated 9 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- A dynamic verification library for Chisel.☆160Updated last year
- An Open-Source Tool for CGRA Accelerators☆82Updated 5 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago