Tests for example Rocket Custom Coprocessors
☆75Feb 19, 2020Updated 6 years ago
Alternatives and similar repositories for rocket-rocc-examples
Users that are interested in rocket-rocc-examples are comparing it to the libraries listed below
Sorting:
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- ☆80Feb 27, 2024Updated 2 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆12Aug 19, 2018Updated 7 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- Chisel Learning Journey☆109Apr 5, 2023Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 4 years ago
- A template project for beginning new Chisel work☆692Feb 24, 2026Updated last week
- ☆14Aug 31, 2025Updated 6 months ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Oct 2, 2019Updated 6 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Support for Rocket Chip on Zynq FPGAs☆416Jan 29, 2019Updated 7 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- ☆26Sep 3, 2020Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Feb 25, 2026Updated last week
- riscv-linux musl gcc toolchain bootstrap scripts☆18Feb 16, 2021Updated 5 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Rocket Chip Generator☆3,696Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- ☆110Oct 19, 2018Updated 7 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Jan 12, 2023Updated 3 years ago
- educational microarchitectures for risc-v isa☆67Feb 18, 2019Updated 7 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,149Updated this week
- Flexible Intermediate Representation for RTL