freechipsproject / chisel-coverageLinks
A coverage library for Chisel designs
☆11Updated 5 years ago
Alternatives and similar repositories for chisel-coverage
Users that are interested in chisel-coverage are comparing it to the libraries listed below
Sorting:
- ☆14Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated this week
- Wrapper for ETH Ariane Core☆21Updated 2 weeks ago
- Useful utilities for BAR projects☆32Updated last year
- Fluid Pipelines☆11Updated 7 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- A DMA Controller for RISCV CPUs☆14Updated 10 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆18Updated 5 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- ☆20Updated 4 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- ☆26Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 weeks ago
- A Rocket-based RISC-V superscalar in-order core☆35Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- The home of the Chisel3 website☆21Updated last year
- ☆12Updated 4 years ago
- Advanced Debug Interface☆15Updated 7 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago