freechipsproject / chisel-coverage
A coverage library for Chisel designs
☆11Updated 5 years ago
Alternatives and similar repositories for chisel-coverage:
Users that are interested in chisel-coverage are comparing it to the libraries listed below
- ☆13Updated 4 years ago
- Useful utilities for BAR projects☆31Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆10Updated 3 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- ☆26Updated 4 years ago
- Wrapper for ETH Ariane Core☆19Updated last month
- Advanced Debug Interface☆14Updated 3 months ago
- A fault-injection framework using Chisel and FIRRTL☆35Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 2 weeks ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- Simple UVM environment for experimenting with Verilator.☆20Updated 3 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- ☆11Updated 3 years ago
- Fluid Pipelines☆11Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆34Updated last month
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- RISC-V processor☆29Updated 2 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆11Updated last month
- ☆19Updated last month
- BFM Tester for Chisel HDL☆14Updated 3 years ago