Alternatives and similar repositories for esp-isa-sim:

Users that are interested in esp-isa-sim are comparing it to the libraries listed below

• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆55Updated 3 weeks ago
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆19Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆30Updated this week
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆30Updated last week
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• pulp-platform / redmule
  ☆47Updated this week
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆70Updated 5 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆38Updated 3 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆31Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• Reconfigurable-Computing / HLStoFPGA
  ☆12Updated 2 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆47Updated last month
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆37Updated 6 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 4 months ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆34Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• sequencer / arithmetic
  ☆32Updated 3 weeks ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last week
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆14Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆28Updated 3 years ago