ucb-bar / esp-isa-simLinks
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
☆17Updated 2 years ago
Alternatives and similar repositories for esp-isa-sim
Users that are interested in esp-isa-sim are comparing it to the libraries listed below
Sorting:
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated this week
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 months ago
- ☆12Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated last week
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Useful utilities for BAR projects☆31Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆15Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last week
- CNN accelerator☆27Updated 8 years ago
- Floating point modules for CHISEL☆32Updated 10 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 7 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- The home of the Chisel3 website☆20Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- The PE for the second generation CGRA (garnet).☆17Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated last week
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago