ucb-bar / nvdla-wrapperLinks
Wraps the NVDLA project for Chipyard integration
☆21Updated 2 weeks ago
Alternatives and similar repositories for nvdla-wrapper
Users that are interested in nvdla-wrapper are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- ☆27Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- ☆19Updated 2 weeks ago
- Fast Floating Point Operators for High Level Synthesis☆22Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated last week
- Chisel Cheatsheet☆33Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated last month
- ☆76Updated this week
- Wrapper for ETH Ariane Core☆21Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- ☆29Updated 3 weeks ago
- ☆29Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- Open Source PHY v2☆30Updated last year
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- ☆13Updated 10 years ago