ucb-bar / nvdla-wrapperLinks
Wraps the NVDLA project for Chipyard integration
☆22Updated 5 months ago
Alternatives and similar repositories for nvdla-wrapper
Users that are interested in nvdla-wrapper are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- ☆29Updated 6 years ago
- The official NaplesPU hardware code repository☆22Updated 6 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆28Updated last week
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- ☆90Updated last week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 3 years ago
- Wrapper for ETH Ariane Core☆22Updated 5 months ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Fast Floating Point Operators for High Level Synthesis☆23Updated 2 years ago
- Chisel Cheatsheet☆35Updated 2 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated last week
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- ☆20Updated last month
- corundum work on vu13p☆23Updated 2 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 11 years ago
- matrix-coprocessor for RISC-V☆30Updated last month
- ☆40Updated 2 years ago