Wraps the NVDLA project for Chipyard integration
☆24Sep 2, 2025Updated last year
Alternatives and similar repositories for nvdla-wrapper
Users that are interested in nvdla-wrapper are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆14Apr 8, 2025Updated last year
- ☆42Oct 26, 2021Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆66Jun 27, 2025Updated last year
- ☆81Feb 27, 2024Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆38Jun 21, 2023Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago
- ☆13Aug 26, 2016Updated 10 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆25Nov 21, 2020Updated 5 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆18Aug 2, 2019Updated 7 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆71Oct 14, 2025Updated 11 months ago
- ☆20Mar 21, 2023Updated 3 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]☆12Jun 15, 2021Updated 5 years ago
- ☆41Jan 23, 2024Updated 2 years ago
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆11Aug 27, 2021Updated 5 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 5 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- ☆13Apr 24, 2015Updated 11 years ago
- Neural Network Accelerator Simulator☆12May 19, 2016Updated 10 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆17Aug 31, 2026Updated 3 weeks ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Apr 5, 2022Updated 4 years ago
- This is a circular buffer controller used in FPGA.☆36Jan 12, 2016Updated 10 years ago
- https://nnsmith-asplos.rtfd.io Artifact of "NNSmith: Generating Diverse and Valid Test Cases for Deep Learning Compilers" ASPLOS'23☆11Mar 29, 2023Updated 3 years ago
- An Open Source FPGA GroestlCoin Miner☆10Feb 11, 2018Updated 8 years ago
- ☆28Dec 4, 2025Updated 9 months ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Updated this week
- RISC-V System on Chip Template☆162Aug 26, 2026Updated 3 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 5 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆31May 10, 2020Updated 6 years ago
- ☆12Aug 4, 2022Updated 4 years ago
- Board files for building PYNQ linux for Zybo☆14Mar 30, 2019Updated 7 years ago