hyoukjun / OpenSMARTLinks
Public release
☆57Updated 5 years ago
Alternatives and similar repositories for OpenSMART
Users that are interested in OpenSMART are comparing it to the libraries listed below
Sorting:
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆77Updated 10 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Project repo for the POSH on-chip network generator☆49Updated 5 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- An integrated CGRA design framework☆90Updated 5 months ago
- ☆26Updated last year
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- ☆44Updated 11 months ago
- ☆12Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆52Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated 2 months ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆18Updated 9 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- ☆34Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- Pure digital components of a UCIe controller☆67Updated last month
- ☆66Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆56Updated 3 weeks ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 11 months ago