Public release
☆58Sep 3, 2019Updated 6 years ago
Alternatives and similar repositories for OpenSMART
Users that are interested in OpenSMART are comparing it to the libraries listed below
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆176Jun 18, 2020Updated 5 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆12Jan 28, 2019Updated 7 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- HNoCS: Modular Open-Source Simulator for Heterogeneous NoCs.☆12Dec 12, 2022Updated 3 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Feb 22, 2018Updated 8 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- SoCRocket - Core Repository☆38Mar 6, 2017Updated 9 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- ☆21Mar 11, 2026Updated last week
- ☆10Apr 8, 2021Updated 4 years ago
- MAESTRO binary release☆22Nov 14, 2019Updated 6 years ago
- ☆34Feb 17, 2026Updated last month
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- MAERI public release☆31Sep 8, 2021Updated 4 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated 3 weeks ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Mar 13, 2026Updated last week
- ☆61Aug 30, 2021Updated 4 years ago
- Network on Chip Simulator☆306Oct 26, 2025Updated 4 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 8 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆165Jan 16, 2022Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- ☆224Jun 25, 2025Updated 8 months ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- Gem5 with PCI Express integrated.☆23Sep 29, 2018Updated 7 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Mar 11, 2026Updated last week
- ☆97Mar 5, 2026Updated 2 weeks ago
- Towards Hardware and Software Continuous Integration☆13Jun 8, 2020Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- A Fast, Low-Overhead On-chip Network☆272Updated this week
- ☆29Aug 4, 2025Updated 7 months ago