hyoukjun / OpenSMARTLinks
Public release
☆52Updated 5 years ago
Alternatives and similar repositories for OpenSMART
Users that are interested in OpenSMART are comparing it to the libraries listed below
Sorting:
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated this week
- ☆34Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆63Updated 5 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- ☆75Updated 10 years ago
- ☆26Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 9 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Project repo for the POSH on-chip network generator☆46Updated 3 months ago
- ☆27Updated 5 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆11Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- MAERI public release☆31Updated 3 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆13Updated 8 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- ☆42Updated 9 months ago
- An integrated CGRA design framework☆89Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 2 months ago
- MAESTRO binary release☆23Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆30Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago