zhemao / riscv-dma3
The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
☆26Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-dma3
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- ☆21Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 8 months ago
- Chisel Cheatsheet☆31Updated last year
- Platform Level Interrupt Controller☆35Updated 6 months ago
- ☆15Updated 3 years ago
- Advanced Debug Interface☆12Updated last year
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- DDR4 Simulation Project in System Verilog☆32Updated 10 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- ☆75Updated 2 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆12Updated 3 months ago