cnrv / rocket-chip-read

Related projects ⓘ

Alternatives and complementary repositories for rocket-chip-read

• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆125Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆107Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆168Updated 4 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆222Updated 3 weeks ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆177Updated this week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆148Updated 9 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆161Updated 11 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆176Updated 2 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆199Updated 4 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆233Updated 2 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆62Updated 5 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆142Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆266Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆61Updated last week
• sparcians / map
  Modeling Architectural Platform
  ☆167Updated last week
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆96Updated 6 years ago
• ucb-bar / berkeley-hardfloat
  ☆290Updated 2 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆65Updated 5 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆118Updated this week
• RV-BOSC / OpenNoC
  ☆62Updated 3 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆223Updated 3 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆217Updated this week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆379Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆137Updated this week
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆113Updated 9 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆225Updated 3 weeks ago
• sifive / block-inclusivecache-sifive
  ☆75Updated 2 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆115Updated last year