Alternatives and similar repositories for rocket-chip-read

Users that are interested in rocket-chip-read are comparing it to the libraries listed below

• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆105Updated 7 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last month
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆224Updated last month
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆263Updated 3 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆204Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆263Updated 6 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆159Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆76Updated 2 weeks ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆159Updated last year
• RV-BOSC / OpenNoC
  ☆214Updated 5 months ago
• OpenXiangShan / GEM5
  ☆115Updated last week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆322Updated last week
• ucb-bar / berkeley-hardfloat
  ☆359Updated 3 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆186Updated 2 weeks ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆161Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆251Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆191Updated 2 weeks ago
• sparcians / map
  Modeling Architectural Platform
  ☆213Updated this week
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago