cnrv / rocket-chip-read
Comment on the rocket-chip source code
☆177Updated 6 years ago
Alternatives and similar repositories for rocket-chip-read:
Users that are interested in rocket-chip-read are comparing it to the libraries listed below
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆191Updated 2 weeks ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆131Updated last month
- ☆310Updated 6 months ago
- Chisel Learning Journey☆108Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆150Updated last year
- Run rocket-chip on FPGA☆66Updated 4 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 7 months ago
- RISC-V Torture Test☆186Updated 8 months ago
- Chisel examples and code snippets☆248Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆189Updated 2 weeks ago
- A dynamic verification library for Chisel.☆147Updated 4 months ago
- Documentation for RISC-V Spike☆100Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- Instruction Set Generator initially contributed by Futurewei☆274Updated last year
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 6 months ago
- An AXI4 crossbar implementation in SystemVerilog☆138Updated last month
- Verilog Configurable Cache☆174Updated 3 months ago
- ☆169Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆210Updated 5 years ago
- ☆74Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆238Updated 5 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆412Updated last week
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆118Updated last year
- Modeling Architectural Platform☆180Updated 2 weeks ago
- Chisel components for FPGA projects☆122Updated last year