Useful utilities for BAR projects
☆32Jan 3, 2024Updated 2 years ago
Alternatives and similar repositories for barstools
Users that are interested in barstools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Feb 13, 2021Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆89Updated this week
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- ☆12May 20, 2021Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆72Nov 7, 2024Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 7 months ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 2 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 8 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- ☆20Feb 9, 2020Updated 6 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆34Apr 13, 2021Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- ☆80Feb 27, 2024Updated 2 years ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆315Mar 6, 2026Updated last month
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 6 months ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- A programming language for FPGAs.☆20May 5, 2018Updated 7 years ago
- Models of finite automata (DFA, NFA) with support of common operations and easily readable creation of objects☆14Feb 4, 2019Updated 7 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 6 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated 11 months ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- ☆17Mar 17, 2022Updated 4 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago