ucb-bar / barstoolsLinks
Useful utilities for BAR projects
☆32Updated 2 years ago
Alternatives and similar repositories for barstools
Users that are interested in barstools are comparing it to the libraries listed below
Sorting:
- A fault-injection framework using Chisel and FIRRTL☆36Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- ☆87Updated 3 weeks ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 3 years ago
- Chisel/Firrtl execution engine☆155Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆32Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆120Updated 8 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆20Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Provides various testers for chisel users☆100Updated 3 years ago
- The home of the Chisel3 website☆21Updated last year
- ☆68Updated 3 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- ☆15Updated 4 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago