ucb-bar / barstoolsLinks
Useful utilities for BAR projects
☆32Updated last year
Alternatives and similar repositories for barstools
Users that are interested in barstools are comparing it to the libraries listed below
Sorting:
- A fault-injection framework using Chisel and FIRRTL☆37Updated 4 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆50Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆86Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Chisel/Firrtl execution engine☆154Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last month
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- ☆56Updated 3 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- The home of the Chisel3 website☆21Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- An implementation of RISC-V☆43Updated 3 weeks ago
- Provides various testers for chisel users☆100Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago