Implementation of the Snappy compression algorithm as a RoCC accelerator
☆12Jul 29, 2019Updated 6 years ago
Alternatives and similar repositories for compression-accelerator
Users that are interested in compression-accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆22Oct 24, 2020Updated 5 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- ☆80Feb 27, 2024Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 6 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆111Oct 19, 2018Updated 7 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 6 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- eyeriss-chisel3☆41May 2, 2022Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- ☆14May 15, 2023Updated 2 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- pinata-csrf-tool☆13Dec 20, 2019Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆18Oct 5, 2023Updated 2 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- Forward the UDP packages (like what NAT does) and do a simple Xor operation bytes by bytes.☆11Feb 18, 2020Updated 6 years ago
- ☆61Aug 30, 2021Updated 4 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆19Feb 25, 2026Updated last month
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 9 months ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- ☆26Sep 3, 2020Updated 5 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago