Alternatives and similar repositories for fpga-rocket-chip:

Users that are interested in fpga-rocket-chip are comparing it to the libraries listed below

• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆177Updated 6 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆189Updated 2 weeks ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆66Updated 4 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• RV-BOSC / OpenNoC
  ☆131Updated last month
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆184Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆147Updated 4 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆174Updated 3 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 7 months ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆100Updated 6 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆116Updated 4 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆274Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆191Updated 2 weeks ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆57Updated last week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆138Updated last month
• OpenXiangShan / GEM5
  ☆74Updated this week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆169Updated last year
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆133Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆79Updated last week
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆117Updated 9 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆88Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 8 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆248Updated 2 years ago