Alternatives and similar repositories for fpga-rocket-chip:

Users that are interested in fpga-rocket-chip are comparing it to the libraries listed below

• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆193Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 5 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆175Updated 4 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆117Updated 4 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆64Updated 10 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆144Updated 2 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆212Updated 4 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆171Updated last year
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆100Updated 6 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆193Updated 3 weeks ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆120Updated 9 years ago
• OpenXiangShan / GEM5
  ☆80Updated this week
• ucb-bar / sha3
  ☆79Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆195Updated last week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆151Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆82Updated 3 weeks ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆145Updated 3 weeks ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 8 months ago