This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.
☆12Aug 19, 2018Updated 7 years ago
Alternatives and similar repositories for Rocket-Chip-RoCC
Users that are interested in Rocket-Chip-RoCC are comparing it to the libraries listed below
Sorting:
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 6 years ago
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆11Apr 21, 2024Updated last year
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- Custom Coprocessor Interface for VexRiscv☆10Sep 19, 2018Updated 7 years ago
- ☆80Feb 27, 2024Updated 2 years ago
- A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.☆18Nov 26, 2014Updated 11 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- riscv-linux musl gcc toolchain bootstrap scripts☆18Feb 16, 2021Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Dec 10, 2018Updated 7 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Chisel Learning Journey☆109Apr 5, 2023Updated 2 years ago
- A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model☆28Sep 25, 2013Updated 12 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Feb 6, 2023Updated 3 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- ☆29Oct 4, 2017Updated 8 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆44Oct 31, 2025Updated 4 months ago
- ☆10Nov 14, 2022Updated 3 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- ☆38Updated this week
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆33May 1, 2021Updated 4 years ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 5 years ago
- Smart Object Oriented Operating system is a lightweight and full featured operating system devoted to embedded systems, currently mainly …☆13Feb 16, 2026Updated 2 weeks ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 7 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- ☆11May 8, 2022Updated 3 years ago
- This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.☆11Aug 1, 2024Updated last year
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- General purpose RF IQ modulator using VGA graphics DAC☆11May 16, 2016Updated 9 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year