ucb-bar / berkeley-hardfloat
☆302Updated 5 months ago
Alternatives and similar repositories for berkeley-hardfloat:
Users that are interested in berkeley-hardfloat are comparing it to the libraries listed below
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 5 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆454Updated this week
- Chisel examples and code snippets☆242Updated 2 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆233Updated 9 months ago
- Instruction Set Generator initially contributed by Futurewei☆271Updated last year
- ☆225Updated 2 years ago
- RISC-V Torture Test☆177Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆243Updated this week
- VeeR EL2 Core☆263Updated this week
- Common SystemVerilog components☆570Updated last week
- Simple RISC-V 3-stage Pipeline in Chisel☆559Updated 6 months ago
- RISC-V CPU Core☆307Updated 8 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆220Updated 2 months ago
- Provides various testers for chisel users☆101Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆241Updated 3 months ago
- A dynamic verification library for Chisel.☆145Updated 3 months ago
- Comment on the rocket-chip source code☆170Updated 6 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆209Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆182Updated 2 months ago
- Common RTL blocks used in SiFive's projects☆181Updated 2 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆353Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆395Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆399Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆166Updated 6 months ago
- Verilog Configurable Cache☆169Updated 2 months ago
- Provides dot visualizations of chisel/firrtl circuits☆120Updated last year
- Build Customized FPGA Implementations for Vivado☆302Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 3 months ago