☆394Aug 19, 2026Updated 2 months ago
Alternatives and similar repositories for berkeley-hardfloat
Users that are interested in berkeley-hardfloat are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆647Sep 14, 2026Updated last month
- Open source high performance IEEE-754 floating unit☆100Feb 26, 2024Updated 2 years ago
- ☆92Oct 20, 2026Updated last week
- A Library of Chisel3 Tools for Digital Signal Processing☆251Apr 29, 2024Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,441Oct 17, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,273Oct 8, 2026Updated 3 weeks ago
- Berkeley's Spatial Array Generator☆1,535Updated this week
- Rocket Chip Generator☆3,892Sep 13, 2026Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆620Aug 9, 2024Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆239Nov 7, 2025Updated 11 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆46Apr 2, 2025Updated last year
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated 2 years ago
- A template project for beginning new Chisel work☆710Feb 24, 2026Updated 8 months ago
- RISC-V Torture Test☆226Jul 11, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- TestFloat release 3☆80Mar 7, 2025Updated last year
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- Chisel: A Modern Hardware Design Language☆4,825Updated this week
- The OpenPiton Platform☆837Updated this week
- educational microarchitectures for risc-v isa☆758Sep 1, 2025Updated last year
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- chisel tutorial exercises and answers☆758Jan 6, 2022Updated 4 years ago
- synthesiseable ieee 754 floating point library in verilog☆763Mar 13, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Heterogeneous GPU Platform for AI and Neural Graphics☆71Updated this week
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- ☆28Dec 4, 2025Updated 10 months ago
- Digital Design with Chisel☆944Updated this week
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 11 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,177Updated this week
- Common SystemVerilog components☆810Sep 18, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆560Oct 16, 2026Updated last week
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆81Feb 27, 2024Updated 2 years ago
- A Linux-capable RISC-V multicore for and by the world☆839Oct 14, 2026Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,317Oct 20, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,214Updated this week
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- Hardfloat using chisel3☆16Sep 23, 2020Updated 6 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,739Updated this week