freechipsproject / firrtl-interpreter
A scala based simulator for circuits described by a LoFirrtl file
☆48Updated 2 years ago
Alternatives and similar repositories for firrtl-interpreter
Users that are interested in firrtl-interpreter are comparing it to the libraries listed below
Sorting:
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Chisel/Firrtl execution engine☆153Updated 8 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated last week
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆55Updated 4 years ago
- The specification for the FIRRTL language☆54Updated this week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- ☆102Updated 2 years ago
- (System)Verilog to Chisel translator☆113Updated 2 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Useful utilities for BAR projects☆31Updated last year
- ☆46Updated last week
- A dynamic verification library for Chisel.☆150Updated 6 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated last week
- Chisel components for FPGA projects☆123Updated last year
- ☆55Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Lipsi: Probably the Smallest Processor in the World☆84Updated last year
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- A prototype GUI for chisel-development☆52Updated 4 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated last week
- ☆66Updated 2 years ago