ucb-bar / OpenSoCFabricLinks
OpenSoC Fabric - A Network-On-Chip Generator
☆18Updated 8 years ago
Alternatives and similar repositories for OpenSoCFabric
Users that are interested in OpenSoCFabric are comparing it to the libraries listed below
Sorting:
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- ☆38Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Advanced Debug Interface☆14Updated 10 months ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 10 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Open Source PHY v2☆31Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- ☆31Updated 2 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- ☆40Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- ☆33Updated 3 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 4 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago