OpenSoC Fabric - A Network-On-Chip Generator
☆18Jun 12, 2017Updated 9 years ago
Alternatives and similar repositories for OpenSoCFabric
Users that are interested in OpenSoCFabric are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆81Feb 27, 2024Updated 2 years ago
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- SystemVerilog stuff and stuff.☆12Jun 2, 2016Updated 10 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 9 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog file list pruner☆19Sep 14, 2026Updated last week
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- ☆18Jun 22, 2026Updated 3 months ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 3 years ago
- Blackwire SpinalHDL components implementing WireGuard primitives☆16Aug 16, 2023Updated 3 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆15Jul 20, 2026Updated 2 months ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- Equivalence checking with Yosys☆64Sep 16, 2026Updated last week
- ☆91Aug 14, 2026Updated last month
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- ☆39Jul 11, 2022Updated 4 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 4 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 11 years ago
- Add support for debugging JITed code to ORC JIT from LLVM Kaleidoscope example☆13Jun 14, 2017Updated 9 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- Public release☆60Sep 3, 2019Updated 7 years ago
- A programming language for FPGAs.☆19May 5, 2018Updated 8 years ago
- ☆387Apr 18, 2018Updated 8 years ago
- Coverview☆35Sep 10, 2026Updated last week
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated 2 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Aug 31, 2026Updated 3 weeks ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆25Nov 15, 2021Updated 4 years ago
- simple hyperram controller☆12Feb 10, 2019Updated 7 years ago