Alternatives and similar repositories for OpenSoCFabric

Users that are interested in OpenSoCFabric are comparing it to the libraries listed below

• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 10 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆34Updated 9 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated last month
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 2 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆40Updated last week
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated last year
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆22Updated 3 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated last week
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 10 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 10 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year