ucb-bar / fpga-zynqLinks
Support for Rocket Chip on Zynq FPGAs
☆409Updated 6 years ago
Alternatives and similar repositories for fpga-zynq
Users that are interested in fpga-zynq are comparing it to the libraries listed below
Sorting:
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆361Updated 7 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆426Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,080Updated 3 weeks ago
- educational microarchitectures for risc-v isa☆715Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆501Updated 4 months ago
- Bus bridges and other odds and ends☆568Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆581Updated 10 months ago
- Common SystemVerilog components☆627Updated this week
- chisel tutorial exercises and answers☆730Updated 3 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆545Updated 2 months ago
- RISC-V CPU Core☆337Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆581Updated last week
- SystemC/TLM-2.0 Co-simulation framework☆247Updated last month
- The root repo for lowRISC project and FPGA demos.☆602Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,308Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 3 weeks ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆320Updated 6 months ago
- Random instruction generator for RISC-V processor verification☆1,135Updated 2 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆497Updated 6 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆556Updated 2 weeks ago
- VeeR EH1 core☆883Updated 2 years ago
- RISC-V Formal Verification Framework☆602Updated 3 years ago
- RISC-V SystemC-TLM simulator☆311Updated 6 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆435Updated this week
- A directory of Western Digital’s RISC-V SweRV Cores☆869Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆643Updated 2 years ago
- The OpenPiton Platform☆710Updated last month
- ☆328Updated 9 months ago
- Digital Design with Chisel☆842Updated last month