Support for Rocket Chip on Zynq FPGAs
☆417Jan 29, 2019Updated 7 years ago
Alternatives and similar repositories for fpga-zynq
Users that are interested in fpga-zynq are comparing it to the libraries listed below
Sorting:
- Rocket Chip Generator☆3,705Feb 25, 2026Updated last week
- Support for Rocket Chip on Zynq FPGAs☆40Apr 24, 2019Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,160Updated this week
- chisel tutorial exercises and answers☆748Jan 6, 2022Updated 4 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- ☆80Feb 27, 2024Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,090Feb 5, 2026Updated last month
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- educational microarchitectures for risc-v isa☆741Sep 1, 2025Updated 6 months ago
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 6 years ago
- Chisel: A Modern Hardware Design Language☆4,598Feb 28, 2026Updated last week
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆685Jul 16, 2025Updated 7 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,001Feb 25, 2026Updated last week
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 2 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,057Feb 14, 2026Updated 3 weeks ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- A template project for beginning new Chisel work☆693Feb 24, 2026Updated last week
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆107Nov 14, 2018Updated 7 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,181Dec 22, 2022Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,837Updated this week
- Examples for creating AXI-interfaced peripherals in Chisel☆75Nov 15, 2015Updated 10 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆65Mar 21, 2023Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,048Feb 11, 2026Updated 3 weeks ago
- A template for building new projects/platforms using the BOOM core.☆25Jan 14, 2019Updated 7 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆60Oct 1, 2023Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Feb 18, 2019Updated 7 years ago
- An open-source microcontroller system based on RISC-V☆1,012Feb 6, 2024Updated 2 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,113Sep 10, 2024Updated last year
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Oct 2, 2019Updated 6 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆165Jan 16, 2022Updated 4 years ago