Alternatives and similar repositories for fpga-zynq

Users that are interested in fpga-zynq are comparing it to the libraries listed below

• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆362Updated 8 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆550Updated 2 weeks ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆871Updated 5 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆718Updated 4 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆272Updated 5 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆359Updated last month
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 2 weeks ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,098Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆512Updated 5 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆252Updated 2 months ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆314Updated 7 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆586Updated 11 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆505Updated 8 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• ucb-bar / berkeley-hardfloat
  ☆334Updated 10 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆240Updated 2 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆258Updated 6 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆721Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆885Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆364Updated 2 weeks ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆213Updated 5 years ago