Alternatives and similar repositories for fpga-zynq

Users that are interested in fpga-zynq are comparing it to the libraries listed below

• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆364Updated 8 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆723Updated 2 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 5 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆872Updated 5 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆561Updated 2 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆392Updated 4 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆598Updated last year
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated 3 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆733Updated 3 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆519Updated 11 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆329Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆539Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆740Updated last month
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆600Updated 2 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆258Updated 5 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆904Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,136Updated 5 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆602Updated 6 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated last week
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆672Updated 2 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆748Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,189Updated last month
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆342Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆613Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆870Updated this week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆688Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago