zhemao / creekView external linksLinks
A vector processor implemented in Chisel
☆21Aug 3, 2014Updated 11 years ago
Alternatives and similar repositories for creek
Users that are interested in creek are comparing it to the libraries listed below
Sorting:
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- ☆11Jan 21, 2019Updated 7 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Feb 22, 2018Updated 7 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- A programming language for FPGAs.☆20May 5, 2018Updated 7 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- Custom Coprocessor Interface for VexRiscv☆10Sep 19, 2018Updated 7 years ago
- ☆82Feb 27, 2024Updated last year
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 6 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- ☆10Jun 9, 2022Updated 3 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel☆16Nov 15, 2024Updated last year
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated last year
- Submission template for Tiny Tapeout 04☆17Jun 15, 2024Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 8 years ago
- Development and simulation framework for Application Specific Vector Processor☆16Mar 8, 2020Updated 5 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆129May 16, 2025Updated 9 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- A collection of notes related to RISC-V before they are processed and digested☆18Dec 19, 2017Updated 8 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated last year
- ☆22Oct 24, 2020Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- Chisel implementation of AES☆24Mar 27, 2020Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago