ucb-bar / riscv-miniLinks
Simple RISC-V 3-stage Pipeline in Chisel
☆602Updated last year
Alternatives and similar repositories for riscv-mini
Users that are interested in riscv-mini are comparing it to the libraries listed below
Sorting:
- A template project for beginning new Chisel work☆677Updated 3 months ago
- educational microarchitectures for risc-v isa☆728Updated 3 months ago
- Digital Design with Chisel☆889Updated last month
- chisel tutorial exercises and answers☆739Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,095Updated last year
- Chisel examples and code snippets☆263Updated 3 years ago
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆370Updated 8 years ago
- ☆362Updated 3 months ago
- Flexible Intermediate Representation for RTL☆749Updated last year
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆327Updated 7 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆554Updated 2 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- Support for Rocket Chip on Zynq FPGAs☆413Updated 6 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆481Updated last month
- The OpenPiton Platform☆749Updated 3 months ago
- VeeR EH1 core☆915Updated 2 years ago
- RISC-V Formal Verification Framework☆620Updated 3 years ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆503Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,153Updated 7 months ago
- 32-bit Superscalar RISC-V CPU☆1,154Updated 4 years ago
- ☆622Updated this week
- Common SystemVerilog components☆689Updated last week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- RISC-V Cores, SoC platforms and SoCs☆907Updated 4 years ago
- RISC-V CPU Core☆401Updated 6 months ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- ☆1,093Updated 3 weeks ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- A Linux-capable RISC-V multicore for and by the world☆751Updated last month