Alternatives and similar repositories for riscv-mini

Users that are interested in riscv-mini are comparing it to the libraries listed below

• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆661Updated 3 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆719Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆858Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,066Updated last year
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆258Updated 3 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,091Updated 3 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆729Updated 2 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆341Updated last year
• riscv-non-isa / riscv-arch-test
  ☆588Updated 2 weeks ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆303Updated 7 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆361Updated 8 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆207Updated 3 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆461Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,117Updated 3 months ago
• riscv-software-src / riscv-tests
  ☆1,053Updated 3 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆609Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆524Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆894Updated 2 years ago
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆478Updated last year
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆412Updated 6 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆731Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆654Updated last week
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆896Updated 4 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆375Updated 2 months ago