Alternatives and similar repositories for riscv-mini:

Users that are interested in riscv-mini are comparing it to the libraries listed below

• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆697Updated 5 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆706Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆795Updated last week
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆608Updated last week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆734Updated 4 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆591Updated 2 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,000Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆999Updated 5 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆550Updated this week
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆241Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆301Updated 4 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆836Updated last year
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆335Updated 7 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆450Updated 2 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆915Updated 3 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆229Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆474Updated this week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆397Updated 2 months ago
• riscv-non-isa / riscv-arch-test
  ☆530Updated last week
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆401Updated 5 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆391Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,051Updated 4 months ago
• riscv-software-src / riscv-tests
  ☆924Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆302Updated 7 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆236Updated 2 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆468Updated last week
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆360Updated last year
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆466Updated last month
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆180Updated 2 months ago