ucb-bar / chisel-awl
☆13Updated 4 years ago
Alternatives and similar repositories for chisel-awl:
Users that are interested in chisel-awl are comparing it to the libraries listed below
- A coverage library for Chisel designs☆11Updated 5 years ago
- Advanced Debug Interface☆14Updated 2 months ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ☆11Updated 3 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- Useful utilities for BAR projects☆31Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- Simple MIDAS Examples☆12Updated 6 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- ☆10Updated 3 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆10Updated 6 years ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- Chisel Things for OFDM☆30Updated 4 years ago
- ☆33Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆24Updated last month
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆14Updated 6 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Wishbone <-> AXI converters☆14Updated 9 years ago