Alternatives and similar repositories for chisel-awl

Users that are interested in chisel-awl are comparing it to the libraries listed below

• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 5 months ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• grebe / ofdm
  Chisel Things for OFDM
  ☆32Updated 5 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆18Updated 8 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• ucb-bar / midas-examples
  Simple MIDAS Examples
  ☆12Updated 6 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆28Updated 5 years ago
• lowRISC / uncore
  ☆11Updated 4 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆12Updated 6 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆29Updated last week
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last month
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated 3 weeks ago
• ucb-bar / compress-acc
  ☆14Updated 3 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago