lowRISC / lowrisc-fpgaLinks
Untethered (stand-alone) FPGA implementation of the lowRISC SoC
☆55Updated 6 years ago
Alternatives and similar repositories for lowrisc-fpga
Users that are interested in lowrisc-fpga are comparing it to the libraries listed below
Sorting:
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 10 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- RISC-V Frontend Server☆64Updated 6 years ago
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- ☆63Updated 7 years ago
- OmniXtend cache coherence protocol☆82Updated 8 months ago
- ReconOS - Operating System for Reconfigurable Hardware☆29Updated 4 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆114Updated 2 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- A Verilog Synthesis Regression Test☆37Updated 3 weeks ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- ☆27Updated 11 months ago
- OpenFPGA☆34Updated 7 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- ☆114Updated 5 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- A 32-bit Microcontroller featuring a RISC-V core☆160Updated 7 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆86Updated 7 years ago