Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
☆87Oct 9, 2025Updated 4 months ago
Alternatives and similar repositories for FireMarshal
Users that are interested in FireMarshal are comparing it to the libraries listed below
Sorting:
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆313Feb 20, 2026Updated last week
- ☆87Jan 30, 2026Updated last month
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Updated this week
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,149Updated this week
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 4 months ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆37Oct 23, 2019Updated 6 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆60Oct 1, 2023Updated 2 years ago
- ☆80Feb 27, 2024Updated 2 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- A Scala library for Context-Dependent Environments☆51Apr 25, 2024Updated last year
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆461May 15, 2025Updated 9 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- Open-source non-blocking L2 cache☆54Updated this week
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 2 months ago
- Release repo for SONIC and TAILS☆21Jun 12, 2020Updated 5 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆244Apr 29, 2024Updated last year
- Berkeley's Spatial Array Generator☆1,225Updated this week
- The specification for the FIRRTL language☆62Updated this week
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- OpenPOWER Foundation General Information & Repository Listing☆25Mar 28, 2022Updated 3 years ago
- A libgloss replacement for RISC-V that supports HTIF☆43May 3, 2024Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆162Jan 25, 2024Updated 2 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.☆45Sep 1, 2025Updated 6 months ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- Support for Rocket Chip on Zynq FPGAs☆416Jan 29, 2019Updated 7 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆286Feb 22, 2026Updated last week