Alternatives and similar repositories for FireMarshal:

Users that are interested in FireMarshal are comparing it to the libraries listed below

• ucb-bar / testchipip
  ☆82Updated this week
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 7 months ago
• riscv / riscv-bfloat16
  ☆33Updated 8 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆172Updated 8 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆150Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆155Updated 4 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆99Updated 5 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆55Updated last month
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆109Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆118Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆249Updated 3 weeks ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆88Updated last week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆129Updated 2 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆147Updated 4 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆88Updated last year
• ucb-bar / sha3
  ☆78Updated last year
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated 2 weeks ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago