Alternatives and similar repositories for FireMarshal:

Users that are interested in FireMarshal are comparing it to the libraries listed below

• ucb-bar / testchipip
  ☆84Updated this week
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 8 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• ucb-bar / sha3
  ☆80Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆153Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆146Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 9 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆65Updated 10 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆39Updated 6 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• riscv / riscv-bfloat16
  ☆35Updated 9 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆92Updated this week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆105Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last month
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆157Updated 10 months ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆59Updated 2 months ago
• CMU-SAFARI / SoftMC
  SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…
  ☆131Updated last year