firesim / FireMarshalLinks
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
☆87Updated 3 months ago
Alternatives and similar repositories for FireMarshal
Users that are interested in FireMarshal are comparing it to the libraries listed below
Sorting:
- ☆87Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- Chisel/Firrtl execution engine☆155Updated last year
- Provides various testers for chisel users☆100Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Next generation CGRA generator☆118Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆183Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- ☆82Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆42Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆129Updated 4 months ago
- Open-source high-performance non-blocking cache☆92Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆60Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- high-performance RTL simulator☆186Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆110Updated 4 months ago
- The Task Parallel System Composer (TaPaSCo)☆116Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆194Updated 4 months ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆143Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆119Updated 2 months ago
- Chisel Learning Journey☆111Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 weeks ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year