dpaletti / dovadoLinks
CLI tool for RTL design space exploration on top of Vivado
☆15Updated 2 years ago
Alternatives and similar repositories for dovado
Users that are interested in dovado are comparing it to the libraries listed below
Sorting:
- VHDL dependency analyzer☆24Updated 5 years ago
- Running Python code in SystemVerilog☆70Updated 2 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- Generated files from ANTLR4 for Verilog parsing in Python☆12Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 3 months ago
- SystemVerilog Linter based on pyslang☆31Updated 4 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Import and export IP-XACT XML register models☆35Updated 2 months ago
- ☆30Updated 2 weeks ago
- SystemVerilog FSM generator☆32Updated last year
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆57Updated 2 months ago
- Open Source Verification Bundle for VHDL and System Verilog☆45Updated last year
- Cross EDA Abstraction and Automation☆39Updated last month
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆46Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- Python library for parsing module definitions and instantiations from SystemVerilog files☆23Updated 4 years ago
- UVM Python Verification Agents Library☆15Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Extended and external tests for Verilator testing☆16Updated last week
- Open Source PHY v2☆29Updated last year
- SystemVerilog Logger☆18Updated 2 years ago
- ☆31Updated last year
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Updated last year
- Python Tool for UVM Testbench Generation☆54Updated last year
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago