spcl / gemm_hlsLinks
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
☆352Updated 6 months ago
Alternatives and similar repositories for gemm_hls
Users that are interested in gemm_hls are comparing it to the libraries listed below
Sorting:
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆322Updated 6 months ago
- Vitis HLS Library for FINN☆204Updated this week
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- Vitis_Accel_Examples☆553Updated last month
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆426Updated 5 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆218Updated 6 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆276Updated 3 months ago
- IC implementation of Systolic Array for TPU☆263Updated 9 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- ☆703Updated last month
- DPU on PYNQ☆225Updated last year
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆276Updated 5 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- Deep Learning Accelerator (Convolution Neural Networks)☆189Updated 7 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆224Updated 4 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- AMD University Program HLS tutorial☆99Updated 9 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆156Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆148Updated this week
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 6 years ago
- IC implementation of TPU☆128Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆350Updated last year
- Network on Chip Simulator☆283Updated 2 weeks ago
- A convolutional neural network implemented in hardware (verilog)☆159Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆106Updated 7 years ago