spcl / gemm_hlsLinks
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
☆365Updated 9 months ago
Alternatives and similar repositories for gemm_hls
Users that are interested in gemm_hls are comparing it to the libraries listed below
Sorting:
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆330Updated 9 months ago
- Vitis HLS Library for FINN☆208Updated 3 weeks ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆201Updated 3 years ago
- Vitis_Accel_Examples☆562Updated 2 months ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆433Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆224Updated 2 years ago
- DPU on PYNQ☆228Updated 2 months ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆224Updated 6 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆236Updated last month
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆279Updated 5 years ago
- ☆732Updated 4 months ago
- IC implementation of Systolic Array for TPU☆285Updated last year
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- Deep Learning Accelerator (Convolution Neural Networks)☆194Updated 7 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆284Updated 2 weeks ago
- Convolutional accelerator kernel, target ASIC & FPGA☆230Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆161Updated 6 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 7 years ago
- AMD University Program HLS tutorial☆116Updated 11 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆173Updated 5 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆332Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆511Updated 6 years ago
- ☆117Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- A convolutional neural network implemented in hardware (verilog)☆163Updated 8 years ago