spcl / gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
☆324Updated last month
Alternatives and similar repositories for gemm_hls:
Users that are interested in gemm_hls are comparing it to the libraries listed below
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆314Updated last month
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- Vitis HLS Library for FINN☆189Updated 3 weeks ago
- Vitis_Accel_Examples☆524Updated this week
- ☆642Updated 3 months ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- DPU on PYNQ☆209Updated last year
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆409Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆210Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 3 months ago
- ☆116Updated 3 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆208Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆173Updated 7 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆263Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆181Updated last year
- A convolutional neural network implemented in hardware (verilog)☆156Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- ☆121Updated 2 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆133Updated 5 years ago
- FPGA Accelerator for CNN using Vivado HLS☆310Updated 3 years ago
- IC implementation of Systolic Array for TPU☆189Updated 4 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆129Updated last month
- Dataflow QNN inference accelerator examples on FPGAs☆199Updated last month
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆164Updated this week
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆141Updated 8 months ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆303Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆108Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆139Updated 5 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆226Updated 6 years ago