template-hls / template-hls-floatLinks
☆29Updated 6 years ago
Alternatives and similar repositories for template-hls-float
Users that are interested in template-hls-float are comparing it to the libraries listed below
Sorting:
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆35Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆71Updated 2 years ago
- ☆24Updated 4 years ago
- DASS HLS Compiler☆29Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆30Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 8 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆23Updated 2 years ago
- ☆58Updated 5 years ago
- ☆59Updated last month
- ☆33Updated 6 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 9 months ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆35Updated 2 months ago
- ☆58Updated last year
- ☆15Updated 2 years ago