☆30Apr 26, 2019Updated 7 years ago
Alternatives and similar repositories for template-hls-float
Users that are interested in template-hls-float are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 6 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆343Jan 20, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆11May 30, 2024Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 4 years ago
- ☆21Jan 31, 2026Updated 6 months ago
- FPGA version of Rodinia in HLS C/C++☆44Dec 24, 2020Updated 5 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆387Jan 20, 2025Updated last year
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆11Mar 13, 2026Updated 4 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆243Dec 8, 2022Updated 3 years ago
- FPGArduino binary☆13Aug 5, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Smith-Waterman Acceleration on Intel’s FPGA with OpenCL for Long DNA Sequences☆19Jan 25, 2019Updated 7 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆208Nov 14, 2021Updated 4 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆22Apr 17, 2024Updated 2 years ago
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆193Mar 8, 2026Updated 5 months ago
- GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and comp…☆15Apr 6, 2022Updated 4 years ago
- Synthesizable Higher-Order Functions (Patterns) for C++☆18Oct 3, 2018Updated 7 years ago
- Updated version of the XUP Workshops☆18Aug 10, 2018Updated 8 years ago
- ☆22Sep 27, 2022Updated 3 years ago
- Vitis HLS Library for FINN☆226May 27, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Systolic array implementations for Cholesky, LU, and QR decomposition☆50Nov 12, 2024Updated last year
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆78Jul 2, 2020Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆173Nov 7, 2023Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs☆19May 23, 2024Updated 2 years ago
- ☆16Mar 2, 2021Updated 5 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Fast Floating Point Operators for High Level Synthesis☆26Feb 23, 2023Updated 3 years ago
- Models and examples built with hls4ml☆12Apr 8, 2020Updated 6 years ago
- ☆26Dec 1, 2020Updated 5 years ago
- BLAS implementation for Intel FPGA☆78Nov 18, 2020Updated 5 years ago
- Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: Open Source Repository☆34Nov 8, 2024Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago