Alternatives and similar repositories for hls4ml:

Users that are interested in hls4ml are comparing it to the libraries listed below

• Xilinx / finn
  Dataflow compiler for QNN inference on FPGAs
  ☆792Updated this week
• fastmachinelearning / hls4ml-tutorial
  Tutorial notebooks for hls4ml
  ☆321Updated last week
• danielholanda / LeFlow
  Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
  ☆603Updated 5 years ago
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆531Updated 2 weeks ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆203Updated last month
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆328Updated last month
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆651Updated 3 months ago
• Xilinx / Vitis-AI-Tutorials
  ☆429Updated 8 months ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆412Updated 5 years ago
• Xilinx / Vitis-Tutorials
  Vitis In-Depth Tutorials
  ☆1,332Updated last week
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆814Updated last month
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆311Updated 3 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆436Updated 6 years ago
• Xilinx / Vitis_Libraries
  Vitis Libraries
  ☆937Updated 3 months ago
• dgschwend / zynqnet
  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
  ☆750Updated 7 years ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆265Updated 5 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆190Updated last week
• Xilinx / PYNQ_Workshop
  ☆417Updated 6 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆316Updated last month
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆211Updated last year
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆889Updated 2 weeks ago
• Xilinx / XRT
  Run Time for AIE and FPGA based platforms
  ☆579Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆785Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆880Updated last week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆574Updated last year
• ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA
  Verilog Generator of Neural Net Digit Detector for FPGA
  ☆304Updated 2 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,229Updated last week
• lastweek / fpga_readings
  Recipe for FPGA cooking
  ☆292Updated 5 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,633Updated last week
• vipinkmenon / neuralNetwork
  ☆260Updated last year