IBM / AccDNNLinks
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
☆433Updated 5 years ago
Alternatives and similar repositories for AccDNN
Users that are interested in AccDNN are comparing it to the libraries listed below
Sorting:
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆366Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆194Updated 7 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆280Updated 5 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆366Updated 9 months ago
- Vitis HLS Library for FINN☆208Updated 3 weeks ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆265Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆161Updated 6 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆511Updated 6 years ago
- IC implementation of Systolic Array for TPU☆290Updated last year
- DPU on PYNQ☆228Updated 2 months ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆230Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆173Updated 5 years ago
- A convolutional neural network implemented in hardware (verilog)☆163Updated 8 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆224Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆188Updated last year
- FPGA Accelerator for CNN using Vivado HLS☆325Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- Implementation of CNN using Verilog☆228Updated 8 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆230Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆168Updated last year
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆112Updated 7 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆242Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆332Updated 6 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs (FPGA'17)☆311Updated 4 years ago
- ☆250Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆154Updated last year
- IC implementation of TPU☆135Updated 5 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆236Updated 2 months ago