Alternatives and similar repositories for AccDNN:

Users that are interested in AccDNN are comparing it to the libraries listed below

• LeiWang1999 / ZYNQ-NVDLA
  NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
  ☆321Updated last year
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆324Updated last month
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆209Updated last year
• Xilinx / CHaiDNN
  HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
  ☆325Updated 5 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆167Updated 11 months ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆173Updated 7 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆189Updated 3 weeks ago
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆156Updated 7 years ago
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆310Updated 3 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆133Updated 5 years ago
• JunningWu / Learning-NVDLA-Notes
  NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…
  ☆226Updated 6 years ago
• embedeep / Free-TPU
  Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…
  ☆244Updated last year
• cornell-zhang / bnn-fpga
  Binarized Convolutional Neural Networks on Software-Programmable FPGAs
  ☆303Updated 4 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆189Updated 4 months ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆263Updated 5 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆206Updated 7 years ago
• cxdzyq1110 / NPU_on_FPGA
  在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
  ☆216Updated 6 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆181Updated last year
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆314Updated last month
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆177Updated 8 years ago
• lulinchen / cnn_open
  A hardware implementation of CNN, written by Verilog and synthesized on FPGA
  ☆219Updated 6 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆141Updated 8 months ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆427Updated 6 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆208Updated 5 years ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆872Updated this week
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆524Updated this week
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆210Updated 2 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆356Updated this week
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆227Updated 2 weeks ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆94Updated 6 years ago