IBM / AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
☆397Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for AccDNN
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆306Updated 10 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆304Updated 2 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆261Updated 4 years ago
- Implementation of CNN using Verilog☆185Updated 7 years ago
- A convolutional neural network implemented in hardware (verilog)☆151Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆165Updated 6 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆221Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆158Updated 7 months ago
- FPGA Accelerator for CNN using Vivado HLS☆297Updated 3 years ago
- DPU on PYNQ☆202Updated 9 months ago
- Vitis HLS Library for FINN☆178Updated 2 weeks ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆161Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆119Updated 5 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆207Updated 5 years ago
- Vitis_Accel_Examples☆505Updated 2 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆125Updated 4 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆370Updated this week
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆213Updated 5 years ago
- ☆595Updated 2 weeks ago
- ☆255Updated 2 weeks ago
- CNN accelerator implemented with Spinal HDL☆134Updated 9 months ago
- IC implementation of Systolic Array for TPU☆148Updated 2 weeks ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆323Updated 5 years ago
- RISC-V Integration for PYNQ☆165Updated 5 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆301Updated 6 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆260Updated last week
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆192Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆88Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…