UCLA-VAST / AutoBridgeLinks
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
☆126Updated 2 years ago
Alternatives and similar repositories for AutoBridge
Users that are interested in AutoBridge are comparing it to the libraries listed below
Sorting:
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- An integrated CGRA design framework☆91Updated 7 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- ☆87Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆161Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- Public release☆57Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- ☆44Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Next generation CGRA generator☆116Updated this week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆71Updated 7 months ago
- ☆24Updated 4 years ago
- HLS-based Graph Processing Framework on FPGAs☆151Updated 3 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆218Updated this week
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- ☆72Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- DASS HLS Compiler☆29Updated 2 years ago