Alternatives and similar repositories for AutoBridge:

Users that are interested in AutoBridge are comparing it to the libraries listed below

• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆165Updated this week
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆120Updated 2 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆121Updated this week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆86Updated 4 months ago
• lana555 / dynamatic
  ☆87Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆86Updated 5 months ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆142Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆44Updated last year
• vaughnbetz / COFFE
  ☆41Updated 6 months ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆68Updated 5 years ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆20Updated 6 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 7 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆119Updated 4 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆33Updated last month
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆63Updated 3 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆100Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆58Updated 2 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆63Updated last week
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆71Updated 10 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆52Updated last week
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆55Updated 3 weeks ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆47Updated 3 weeks ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆48Updated 7 years ago