UCLA-VAST / AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
☆198Updated last year
Related projects ⓘ
Alternatives and complementary repositories for AutoSA
- A scalable High-Level Synthesis framework on MLIR☆226Updated 5 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆155Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated this week
- CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture☆123Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆158Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- Repository to host and maintain scale-sim-v2 code☆232Updated this week
- A DSL for Systolic Arrays☆78Updated 5 years ago
- Release of stream-specialization software/hardware stack.☆116Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆220Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆66Updated 3 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆119Updated 5 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆115Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆79Updated last month
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆174Updated 4 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆260Updated last week
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆113Updated this week
- PyTorch model to RTL flow for low latency inference☆121Updated 7 months ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆126Updated 2 months ago
- Vitis HLS Library for FINN☆178Updated 2 weeks ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing☆325Updated 6 months ago
- An integrated CGRA design framework☆83Updated this week
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆168Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆120Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆59Updated 4 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆98Updated last year
- RTL implementation of Flex-DPE.☆89Updated 4 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆55Updated last month
- ☆84Updated 8 months ago