UCLA-VAST / AutoSALinks
AutoSA: Polyhedral-Based Systolic Array Compiler
☆222Updated 2 years ago
Alternatives and similar repositories for AutoSA
Users that are interested in AutoSA are comparing it to the libraries listed below
Sorting:
- A scalable High-Level Synthesis framework on MLIR☆270Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆174Updated last week
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆147Updated 3 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆156Updated last month
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆155Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 10 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆137Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆241Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 4 months ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- Repository to host and maintain SCALE-Sim code☆333Updated last week
- An integrated CGRA design framework☆90Updated 5 months ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆225Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing☆340Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆112Updated 2 years ago
- ☆57Updated 5 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆28Updated 2 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆114Updated 2 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week