UCLA-VAST / AutoSALinks
AutoSA: Polyhedral-Based Systolic Array Compiler
☆236Updated 3 years ago
Alternatives and similar repositories for AutoSA
Users that are interested in AutoSA are comparing it to the libraries listed below
Sorting:
- A scalable High-Level Synthesis framework on MLIR☆286Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆175Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆154Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆150Updated this week
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 6 months ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆165Updated 2 years ago
- An integrated CGRA design framework☆91Updated 9 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆120Updated 2 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆255Updated 3 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆245Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆113Updated 9 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆68Updated 6 years ago
- ☆61Updated 9 months ago
- Repository to host and maintain SCALE-Sim code☆405Updated 3 weeks ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆56Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago