This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
☆20Sep 3, 2019Updated 6 years ago
Alternatives and similar repositories for Zynq_HLS_DDR_Dataflow_kernel_2mm
Users that are interested in Zynq_HLS_DDR_Dataflow_kernel_2mm are comparing it to the libraries listed below
Sorting:
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 7 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆14Feb 16, 2024Updated 2 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last month
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 8 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- general-cores☆21Jul 16, 2025Updated 7 months ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated last month
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆23Oct 29, 2025Updated 4 months ago
- umbrella project helps you to build up onnc from scratch☆24Mar 14, 2022Updated 3 years ago
- The template for VLSI project☆25May 10, 2019Updated 6 years ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆27Feb 7, 2023Updated 3 years ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- ☆24Dec 1, 2020Updated 5 years ago
- ☆19Aug 9, 2022Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 12 years ago
- DASS HLS Compiler☆29Oct 4, 2023Updated 2 years ago
- TCL scripts for FPGA (Xilinx)☆35Jul 5, 2022Updated 3 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)☆33Feb 10, 2020Updated 6 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- ☆13Jan 8, 2020Updated 6 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆40Feb 24, 2025Updated last year
- mirror of https://git.elphel.com/Elphel/eddr3☆41Oct 16, 2017Updated 8 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year