zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mmLinks
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
☆21Updated 5 years ago
Alternatives and similar repositories for Zynq_HLS_DDR_Dataflow_kernel_2mm
Users that are interested in Zynq_HLS_DDR_Dataflow_kernel_2mm are comparing it to the libraries listed below
Sorting:
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- ☆34Updated 6 years ago
- ☆26Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆33Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- ☆20Updated 2 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- ☆14Updated last month
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆15Updated this week
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last week
- ☆59Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- ☆27Updated 5 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- ☆77Updated 10 years ago
- ☆65Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago