zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mm
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
☆21Updated 5 years ago
Alternatives and similar repositories for Zynq_HLS_DDR_Dataflow_kernel_2mm:
Users that are interested in Zynq_HLS_DDR_Dataflow_kernel_2mm are comparing it to the libraries listed below
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- ☆32Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- ☆64Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 11 years ago
- ☆14Updated 2 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- ☆26Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆72Updated last year
- DMA controller for CNN accelerator☆13Updated 7 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆12Updated this week
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- ☆25Updated last year
- understanding of cocotb (In Chinese Only)☆16Updated last year
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- 使用FPGA实现CNN模型☆14Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 8 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago