This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
☆20Sep 3, 2019Updated 6 years ago
Alternatives and similar repositories for Zynq_HLS_DDR_Dataflow_kernel_2mm
Users that are interested in Zynq_HLS_DDR_Dataflow_kernel_2mm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 7 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆17Feb 16, 2024Updated 2 years ago
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆24Oct 29, 2025Updated 5 months ago
- ☆13Jul 2, 2016Updated 9 years ago
- The template for VLSI project☆26May 10, 2019Updated 6 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 6 years ago
- FPGA and CPU-Based power system's simulator☆21Apr 7, 2021Updated 5 years ago
- Test cases for the simulation of electromagnetic transients☆14Jun 26, 2025Updated 9 months ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆28Feb 7, 2023Updated 3 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated last month
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 13 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆16Jun 23, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- umbrella project helps you to build up onnc from scratch☆24Mar 14, 2022Updated 4 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆379Jan 20, 2025Updated last year
- ☆30Mar 26, 2026Updated 2 weeks ago
- Hardware and Software Co-design implementations☆15Dec 5, 2019Updated 6 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 11 years ago
- A Xilinx IP Core and App for line scanner image capture and store☆11Sep 5, 2017Updated 8 years ago
- ☆10Jul 6, 2015Updated 10 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Global Dark Mode for ALL apps on ANY platforms.☆19Oct 3, 2023Updated 2 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆15Mar 21, 2024Updated 2 years ago
- Floating-point matrix multiplication implementation (arbitrary precision)☆17Aug 3, 2021Updated 4 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆66Mar 15, 2022Updated 4 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆14Jul 12, 2023Updated 2 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- ☆24Dec 1, 2020Updated 5 years ago
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 6 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 8 years ago
- ☆19Aug 9, 2022Updated 3 years ago
- general-cores☆21Jul 16, 2025Updated 8 months ago