zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mmLinks
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
☆21Updated 5 years ago
Alternatives and similar repositories for Zynq_HLS_DDR_Dataflow_kernel_2mm
Users that are interested in Zynq_HLS_DDR_Dataflow_kernel_2mm are comparing it to the libraries listed below
Sorting:
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆34Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- ☆75Updated 10 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated last week
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- ☆20Updated 2 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆65Updated 6 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- The template for VLSI project☆19Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago