TomG008 / SkyNetLinks
☆240Updated 3 years ago
Alternatives and similar repositories for SkyNet
Users that are interested in SkyNet are comparing it to the libraries listed below
Sorting:
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆183Updated last year
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- ☆53Updated 5 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- ☆33Updated 6 years ago
- An Open Source Deep Learning Inference Engine Based on FPGA☆158Updated 4 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 6 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆228Updated 6 years ago
- ☆35Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- ☆248Updated 4 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆273Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆72Updated 6 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- 中文:☆101Updated 5 years ago
- using xilinx xc6slx45 to implement mnist net☆83Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆308Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …☆52Updated 2 years ago
- DAC System Design Contest 2020☆29Updated 5 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 7 years ago
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆72Updated last year
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 5 years ago