Xilinx / finn-hlslibLinks
Vitis HLS Library for FINN
☆213Updated 3 weeks ago
Alternatives and similar repositories for finn-hlslib
Users that are interested in finn-hlslib are comparing it to the libraries listed below
Sorting:
- DPU on PYNQ☆241Updated 5 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆374Updated last year
- Dataflow QNN inference accelerator examples on FPGAs☆242Updated 5 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆197Updated 8 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆179Updated 6 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- Convolutional accelerator kernel, target ASIC & FPGA☆242Updated 2 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆75Updated 5 years ago
- ☆124Updated 5 years ago
- AMD University Program HLS tutorial☆123Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆169Updated 6 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆334Updated last year
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆226Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆114Updated 7 years ago
- An LSTM template and a few examples using Vivado HLS☆47Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆48Updated last year
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆282Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆148Updated 11 months ago
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆122Updated last year
- ☆250Updated 5 years ago
- IC implementation of TPU☆147Updated 6 years ago