UCLA-VAST / FlexCNN
☆71Updated 2 years ago
Alternatives and similar repositories for FlexCNN:
Users that are interested in FlexCNN are comparing it to the libraries listed below
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆57Updated 4 years ago
- ☆70Updated 5 years ago
- ☆26Updated last month
- ☆33Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆56Updated 3 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Updated 6 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆34Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆39Updated 10 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- ☆15Updated 10 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆93Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆23Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆29Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆45Updated 2 months ago
- ☆29Updated 6 years ago
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- eyeriss-chisel3☆40Updated 3 years ago