UCLA-VAST / FlexCNNLinks
☆72Updated 2 years ago
Alternatives and similar repositories for FlexCNN
Users that are interested in FlexCNN are comparing it to the libraries listed below
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆71Updated 5 years ago
- A DSL for Systolic Arrays☆81Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 3 months ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆35Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆59Updated 3 years ago
- ☆40Updated last year
- ☆30Updated 6 months ago
- ☆60Updated 5 years ago
- ☆35Updated 6 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆37Updated 6 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated 5 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated 2 weeks ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆69Updated 6 months ago