Xilinx / Vitis-HLS-Introductory-Examples
☆657Updated 4 months ago
Alternatives and similar repositories for Vitis-HLS-Introductory-Examples:
Users that are interested in Vitis-HLS-Introductory-Examples are comparing it to the libraries listed below
- Vitis_Accel_Examples☆532Updated last month
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆331Updated 2 months ago
- ☆279Updated last week
- Verilog AXI stream components for FPGA implementation☆791Updated 3 weeks ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆318Updated 2 months ago
- Vitis In-Depth Tutorials☆1,344Updated this week
- ☆191Updated 2 months ago
- ☆418Updated 6 months ago
- ☆607Updated 8 months ago
- Verilog AXI components for FPGA implementation☆1,655Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,240Updated this week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆316Updated 10 months ago
- Verilog PCI express components☆1,252Updated 10 months ago
- Verilog UART☆461Updated 3 weeks ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆557Updated last year
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆414Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆590Updated 2 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆236Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆591Updated 3 weeks ago
- ☆430Updated 9 months ago
- Vitis Libraries☆947Updated this week
- Vitis HLS Library for FINN☆191Updated last week
- DPU on PYNQ☆214Updated last year
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆814Updated 2 months ago
- AMBA bus lecture material☆414Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆331Updated last year
- Bus bridges and other odds and ends☆526Updated last month
- AXI interface modules for Cocotb☆245Updated last year
- Common SystemVerilog components☆593Updated last week
- Implementation of CNN using Verilog☆209Updated 7 years ago