Xilinx / Vitis-HLS-Introductory-Examples

Related projects ⓘ

Alternatives and complementary repositories for Vitis-HLS-Introductory-Examples

• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆506Updated this week
• Xilinx / Vitis-Tutorials
  Vitis In-Depth Tutorials
  ☆1,248Updated last week
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆307Updated 2 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆745Updated 3 months ago
• Xilinx / PYNQ_Workshop
  ☆402Updated 2 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆303Updated 6 months ago
• Xilinx / XilinxBoardStore
  ☆256Updated this week
• Xilinx / Vitis_Libraries
  Vitis Libraries
  ☆895Updated this week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,518Updated 11 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,113Updated this week
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆795Updated last week
• Digilent / vivado-library
  ☆575Updated 4 months ago
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆299Updated 3 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆181Updated last week
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆202Updated 9 months ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆399Updated 4 years ago
• xupsh / pp4fpgas-cn-hls
  HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
  ☆235Updated 3 years ago
• Xilinx / Vitis-AI-Tutorials
  ☆394Updated 5 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆531Updated last year
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,140Updated 6 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆158Updated this week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆264Updated 6 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆777Updated 5 months ago
• Xilinx / XRT
  Run Time for AIE and FPGA based platforms
  ☆559Updated this week
• alexforencich / verilog-uart
  Verilog UART
  ☆424Updated last year
• Xilinx / Vitis-In-Depth-Tutorial
  ☆116Updated 3 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆379Updated 4 years ago
• Xilinx / CHaiDNN
  HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
  ☆323Updated 5 years ago