An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
☆93Jul 26, 2024Updated last year
Alternatives and similar repositories for Sextans
Users that are interested in Sextans are comparing it to the libraries listed below
Sorting:
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- ☆21Sep 17, 2024Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆183Aug 16, 2025Updated 6 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Sep 27, 2024Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆22Jul 26, 2024Updated last year
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆20Aug 24, 2025Updated 6 months ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 5 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Dec 20, 2022Updated 3 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆164Updated this week
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- ☆19Mar 17, 2021Updated 4 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆16Aug 29, 2021Updated 4 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- ☆60Aug 4, 2023Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 3 years ago
- A graph linear algebra overlay☆52Apr 26, 2023Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆49Nov 12, 2024Updated last year
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆85Nov 7, 2021Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆63Jun 27, 2025Updated 8 months ago
- ☆37Jan 20, 2022Updated 4 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆239Dec 8, 2022Updated 3 years ago
- ☆13Aug 1, 2024Updated last year
- Release of stream-specialization software/hardware stack.☆120May 5, 2023Updated 2 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Apr 20, 2024Updated last year
- ACM TODAES Best Paper Award, 2022☆32Oct 24, 2023Updated 2 years ago
- ☆45Feb 26, 2026Updated last week
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆43Mar 30, 2021Updated 4 years ago
- ☆17Feb 13, 2021Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago