linghaosong / Sextans
An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
☆77Updated 7 months ago
Alternatives and similar repositories for Sextans:
Users that are interested in Sextans are comparing it to the libraries listed below
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 5 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆30Updated this week
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆71Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated last month
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago
- ☆71Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆131Updated this week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 5 months ago
- ☆47Updated last month
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆39Updated 8 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- ☆70Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆16Updated 6 months ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆10Updated last month
- ☆23Updated 7 months ago
- ☆24Updated 4 months ago
- ☆33Updated last week
- A co-design architecture on sparse attention☆50Updated 3 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆125Updated 9 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆62Updated last year