Alternatives and similar repositories for Sextans

Users that are interested in Sextans are comparing it to the libraries listed below

• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 10 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆62Updated 5 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆110Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆26Updated last year
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated last month
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆83Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆58Updated 3 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆57Updated 5 months ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆58Updated this week
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆150Updated this week
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 5 months ago
• maestro-project / gamma
  ☆41Updated last year
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆73Updated 2 years ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• hngenc / stellar
  ☆30Updated 9 months ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 4 months ago
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆137Updated 2 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆77Updated 6 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆56Updated 4 months ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆19Updated last year
• isakedo / DNNsim
  ☆35Updated 5 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆40Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 5 months ago