cornell-zhang / HiSparseLinks
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
☆94Updated 10 months ago
Alternatives and similar repositories for HiSparse
Users that are interested in HiSparse are comparing it to the libraries listed below
Sorting:
- ☆56Updated 4 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆148Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆55Updated 3 weeks ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆76Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆67Updated 4 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- RTL implementation of Flex-DPE.☆107Updated 5 years ago
- ☆72Updated 2 years ago
- gem5 repository to study chiplet-based systems☆77Updated 6 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- ☆30Updated 8 months ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated last year
- An integrated CGRA design framework☆90Updated 4 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆135Updated last month
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆60Updated 7 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆40Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆46Updated 3 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- ☆24Updated 4 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 9 months ago
- ☆92Updated last year