High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
☆98Sep 27, 2024Updated last year
Alternatives and similar repositories for HiSparse
Users that are interested in HiSparse are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A graph linear algebra overlay☆52Apr 26, 2023Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆188Mar 8, 2026Updated last month
- Serpens is an HBM FPGA accelerator for SpMV☆23Jul 26, 2024Updated last year
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆33Nov 12, 2024Updated last year
- A Generic Distributed Auto-Tuning Infrastructure☆24Jul 29, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆338Apr 20, 2024Updated 2 years ago
- ☆11Oct 28, 2021Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆94Jul 26, 2024Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- HLS-based Graph Processing Framework on FPGAs☆151Oct 11, 2022Updated 3 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆55Jul 17, 2023Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆18Aug 29, 2024Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆171Nov 7, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 3 years ago
- GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks☆36Oct 1, 2023Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆382Jan 20, 2025Updated last year
- ☆13Aug 1, 2024Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆99Oct 2, 2021Updated 4 years ago
- A scalable High-Level Synthesis framework on MLIR☆295May 15, 2024Updated last year
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Dec 6, 2020Updated 5 years ago
- ☆17Feb 3, 2023Updated 3 years ago
- Polynormer: Polynomial-Expressive Graph Transformer in Linear Time (ICLR'24)☆42Apr 6, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆16Oct 25, 2022Updated 3 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆15Nov 15, 2022Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- Codebase for ICML'24 paper: Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs☆27Jun 25, 2024Updated last year
- ☆14Feb 14, 2022Updated 4 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆373Mar 13, 2026Updated last month
- ☆72Feb 16, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PyTorch model to RTL flow for low latency inference☆131Mar 15, 2024Updated 2 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆129Dec 20, 2022Updated 3 years ago
- An FPGA Accelerator for Transformer Inference☆93Apr 29, 2022Updated 4 years ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated 2 years ago