Xilinx / gemxLinks
Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
☆63Updated 6 years ago
Alternatives and similar repositories for gemx
Users that are interested in gemx are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆82Updated 11 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 8 years ago
- ☆88Updated 3 years ago
- ☆30Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- HLS branch of Halide☆79Updated 7 years ago
- ☆28Updated 7 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆47Updated 2 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- ☆83Updated 5 years ago
- CNN accelerator☆29Updated 8 years ago
- Next generation CGRA generator☆118Updated this week
- ☆40Updated 6 years ago
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- ☆65Updated 5 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆49Updated 7 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Tutorials on HLS Design☆52Updated 6 years ago
- Caffe to VHDL☆68Updated 5 years ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 weeks ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago