Alternatives and similar repositories for gemx

Users that are interested in gemx are comparing it to the libraries listed below

• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated 5 months ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆166Updated last year
• tukl-msd / LSTM-PYNQ
  ☆28Updated 7 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆200Updated 3 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• Xilinx / SDSoC_Examples
  ☆84Updated 5 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 2 years ago
• jingpu / Halide-HLS
  HLS branch of Halide
  ☆77Updated 7 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆140Updated 5 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• falconcomputing / merlin-compiler
  Falcon Merlin Compiler
  ☆41Updated 5 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆322Updated 6 months ago
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆69Updated 6 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆213Updated 5 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆48Updated last year
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆128Updated 5 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆276Updated 3 months ago
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆48Updated 6 years ago
• fpga-opencl-benchmarks / rodinia_fpga
  Rodinia Benchmark Suite for OpenCL-based FPGAs
  ☆31Updated 2 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 7 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆106Updated 7 years ago