HLS implemented systolic array structure
☆41Nov 13, 2017Updated 8 years ago
Alternatives and similar repositories for systolic-array
Users that are interested in systolic-array are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆73Dec 12, 2018Updated 7 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆385Jan 20, 2025Updated last year
- Implementation of convolution layer in different flavors☆68Oct 8, 2017Updated 8 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆19Jan 17, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆19Mar 21, 2023Updated 3 years ago
- C++ SystemC Implementation of a Systolic Array☆16May 15, 2020Updated 6 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 6 years ago
- ☆24May 30, 2025Updated 11 months ago
- ☆73Feb 16, 2023Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆339Jul 9, 2019Updated 6 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- MAERI public release☆31Sep 8, 2021Updated 4 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆29Jun 8, 2018Updated 7 years ago
- ☆19Mar 17, 2021Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 6 years ago
- A command-line tool for convert SVG image to PDF file☆17Mar 29, 2025Updated last year
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- ☆119Dec 20, 2017Updated 8 years ago
- ☆24Dec 1, 2020Updated 5 years ago
- ☆28Dec 12, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A FPGA Based CNN accelerator, following Google's TPU V1.☆175Jul 25, 2019Updated 6 years ago
- ☆10Sep 3, 2016Updated 9 years ago
- Face recognition, computer vision, deep learning, PYNQ, Movidius NCS☆63Jan 29, 2019Updated 7 years ago
- ☆39May 12, 2017Updated 9 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- Pytorch implementation of SEENN (Spiking Early Exit Neural Networks) (NeurIPS 2023)☆19Nov 18, 2024Updated last year
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆241Dec 8, 2022Updated 3 years ago
- manage my star project on github☆11Jul 23, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Generator of verilog description for FPGA MobileNet implementation☆187Jun 23, 2022Updated 3 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆83Nov 2, 2020Updated 5 years ago
- ☆15Nov 12, 2023Updated 2 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago