Alternatives and similar repositories for systolic-array

Users that are interested in systolic-array are comparing it to the libraries listed below

• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆72Updated 7 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 4 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• awai54st / LUTNet
  ☆64Updated 5 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆96Updated 4 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆50Updated 10 months ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆47Updated last year
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆46Updated last year
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• sharc-lab / FPGA_ECE8893
  ☆39Updated last week
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆36Updated 5 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆33Updated 6 years ago
• fffasttime / AnyPackingNet
  ☆32Updated 9 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• gem5-X / TiC-SAT
  ☆20Updated 8 months ago
• zeasa / nvdla-compiler
  ☆49Updated 6 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated 2 years ago
• CASR-HKU / DPACS
  ☆19Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• groupsada / DeepBurning
  Automatic generation of FPGA-based learning accelerators for the neural network family
  ☆68Updated 6 years ago
• PSCLab-ASU / Systolic-CNN
  ☆17Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 6 months ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆39Updated 5 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago