xliu0709 / WinoCNNLinks
An HLS based winograd systolic CNN accelerator
☆53Updated 3 years ago
Alternatives and similar repositories for WinoCNN
Users that are interested in WinoCNN are comparing it to the libraries listed below
Sorting:
- ☆65Updated 6 years ago
- ☆112Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- ☆71Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆63Updated 5 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆71Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆83Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 3 years ago
- ☆33Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- ☆11Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago