Alternatives and similar repositories for WinoCNN

Users that are interested in WinoCNN are comparing it to the libraries listed below

• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆91Updated 3 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆93Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆68Updated 6 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆34Updated 6 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆86Updated last year
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆48Updated 7 months ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆45Updated last year
• PSCLab-ASU / Systolic-CNN
  ☆17Updated 4 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆33Updated this week
• fffasttime / AnyPackingNet
  ☆30Updated 6 months ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆26Updated 3 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆119Updated 5 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆55Updated 3 years ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆70Updated 3 years ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆12Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆95Updated 8 months ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 6 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆57Updated 3 years ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆26Updated last month