xliu0709 / WinoCNNLinks
An HLS based winograd systolic CNN accelerator
☆52Updated 3 years ago
Alternatives and similar repositories for WinoCNN
Users that are interested in WinoCNN are comparing it to the libraries listed below
Sorting:
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- ☆71Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆56Updated 4 months ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- ☆65Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆82Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 8 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆43Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆27Updated 2 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- ☆33Updated 6 years ago
- ☆71Updated 2 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆16Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month