Xilinx / Vitis_LibrariesLinks
Vitis Libraries
☆1,011Updated 3 weeks ago
Alternatives and similar repositories for Vitis_Libraries
Users that are interested in Vitis_Libraries are comparing it to the libraries listed below
Sorting:
- Vitis In-Depth Tutorials☆1,443Updated 3 weeks ago
- Vitis_Accel_Examples☆556Updated last month
- ☆712Updated 2 months ago
- Run Time for AIE and FPGA based platforms☆628Updated this week
- ☆465Updated last year
- Dataflow compiler for QNN inference on FPGAs☆868Updated last week
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆363Updated 7 months ago
- ☆450Updated last year
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆852Updated 8 months ago
- Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.☆1,653Updated 5 months ago
- 中文版 Parallel Programming for FPGAs☆746Updated last year
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆431Updated 5 years ago
- ☆632Updated last month
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆324Updated 7 months ago
- ☆131Updated 3 months ago
- Xilinx QDMA IP Drivers☆713Updated 3 weeks ago
- ☆222Updated last month
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆508Updated 6 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆859Updated 2 months ago
- DPU on PYNQ☆227Updated last month
- Verilog AXI stream components for FPGA implementation☆830Updated 6 months ago
- Quantized Neural Networks (QNNs) on PYNQ☆701Updated 3 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆873Updated last year
- ☆118Updated 4 years ago
- The RIFFA development repository☆848Updated last year
- ☆295Updated 3 weeks ago
- SDAccel Examples☆359Updated 3 years ago
- A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…☆512Updated 2 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,336Updated 3 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆332Updated 6 years ago