lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
☆37Updated 5 years ago
Alternatives and similar repositories for A-convolution-kernel-implemented-by-Vivado-HLS:
Users that are interested in A-convolution-kernel-implemented-by-Vivado-HLS are comparing it to the libraries listed below
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 6 months ago
- ☆70Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆23Updated 3 years ago
- ☆57Updated 4 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- ☆64Updated 6 years ago
- ☆35Updated 2 weeks ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆31Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- ☆71Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆112Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆42Updated 2 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- ☆33Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆78Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- Template for project1 TPU☆18Updated 3 years ago
- Verilog implementation of Softmax function☆62Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago