This project implements a convolution kernel based on vivado HLS on zcu104
☆36Mar 15, 2020Updated 6 years ago
Alternatives and similar repositories for A-convolution-kernel-implemented-by-Vivado-HLS
Users that are interested in A-convolution-kernel-implemented-by-Vivado-HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Mar 17, 2021Updated 5 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆20Jan 21, 2022Updated 4 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Vitis HLS Library for FINN☆221Feb 25, 2026Updated 2 months ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- ☆19Sep 12, 2022Updated 3 years ago
- Fast Floating Point Operators for High Level Synthesis☆25Feb 23, 2023Updated 3 years ago
- CNN simd based accelerator using Vitis HLS☆11Jul 15, 2022Updated 3 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Sep 23, 2020Updated 5 years ago
- FPGA implementation of a handwritten digit recognition system based on k-nearest-neighbors (k-NN) classifier algorithm.☆21Apr 3, 2018Updated 8 years ago
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 6 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆16Feb 20, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆25Jun 28, 2019Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53May 29, 2018Updated 7 years ago
- ☆11Aug 2, 2024Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆175Jul 25, 2019Updated 6 years ago
- super-resolution; post-training quantization; model compression☆14Nov 10, 2023Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆189Mar 8, 2026Updated 2 months ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Some attempts to build CNN on PYNQ.☆25Jun 28, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆384Jan 20, 2025Updated last year
- ☆74Mar 22, 2020Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93May 25, 2019Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆94Jul 26, 2024Updated last year
- An HBM FPGA based SpMV Accelerator☆18Aug 29, 2024Updated last year
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- ☆244Jun 21, 2022Updated 3 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- TQT's pytorch implementation.☆21Dec 17, 2021Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 8 years ago
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 2 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 4 years ago
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆55Jan 12, 2026Updated 3 months ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago