lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLSLinks
This project implements a convolution kernel based on vivado HLS on zcu104
☆37Updated 5 years ago
Alternatives and similar repositories for A-convolution-kernel-implemented-by-Vivado-HLS
Users that are interested in A-convolution-kernel-implemented-by-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- ☆70Updated 6 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- A collection of tutorials for the fpgaConvNet framework.☆45Updated last year
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- ☆35Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆27Updated 3 years ago
- ☆60Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- ☆17Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- ☆72Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 6 years ago