This project implements a convolution kernel based on vivado HLS on zcu104
☆36Mar 15, 2020Updated 6 years ago
Alternatives and similar repositories for A-convolution-kernel-implemented-by-Vivado-HLS
Users that are interested in A-convolution-kernel-implemented-by-Vivado-HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Mar 17, 2021Updated 5 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Vitis HLS Library for FINN☆229Updated this week
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 5 years ago
- ☆19Sep 12, 2022Updated 4 years ago
- CNN simd based accelerator using Vitis HLS☆12Jul 15, 2022Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Sep 23, 2020Updated 6 years ago
- Fast Floating Point Operators for High Level Synthesis☆26Feb 23, 2023Updated 3 years ago
- FPGA implementation of a handwritten digit recognition system based on k-nearest-neighbors (k-NN) classifier algorithm.☆21Apr 3, 2018Updated 8 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆20Jan 21, 2022Updated 4 years ago
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53May 29, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆16Feb 20, 2017Updated 9 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Jun 28, 2019Updated 7 years ago
- super-resolution; post-training quantization; model compression☆14Nov 10, 2023Updated 2 years ago
- ☆11Aug 2, 2024Updated 2 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated 2 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 7 years ago
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆194Aug 11, 2026Updated 2 months ago
- Some attempts to build CNN on PYNQ.☆25Jun 28, 2019Updated 7 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆390Jan 20, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A FPGA Based CNN accelerator, following Google's TPU V1.☆179Jul 25, 2019Updated 7 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 9 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 9 years ago
- ☆74Mar 22, 2020Updated 6 years ago
- TQT's pytorch implementation.☆22Dec 17, 2021Updated 4 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92May 25, 2019Updated 7 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆96Aug 11, 2026Updated 2 months ago
- ☆246Jun 21, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.☆13Dec 18, 2017Updated 8 years ago
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated 2 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆15Aug 26, 2021Updated 5 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆21Apr 8, 2024Updated 2 years ago