definelicht / hlslibLinks
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
☆319Updated 4 months ago
Alternatives and similar repositories for hlslib
Users that are interested in hlslib are comparing it to the libraries listed below
Sorting:
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆345Updated 4 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- Vitis HLS Library for FINN☆198Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆269Updated last month
- Vitis_Accel_Examples☆540Updated 3 weeks ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆170Updated this week
- DPU on PYNQ☆221Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- ☆288Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- VNx: Vitis Network Examples☆149Updated 10 months ago
- ☆119Updated 3 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆209Updated last year
- ☆126Updated 6 months ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆261Updated last week
- Dataflow QNN inference accelerator examples on FPGAs☆217Updated 2 months ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆216Updated 6 years ago
- ☆684Updated last week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆143Updated this week
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆272Updated 5 years ago
- Board files to build Ultra 96 PYNQ image☆155Updated 5 months ago
- Build Customized FPGA Implementations for Vivado☆322Updated this week
- HLS-based Graph Processing Framework on FPGAs☆145Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆373Updated 3 weeks ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆153Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆192Updated 4 years ago