UCLA-VAST / tapaLinks
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.
☆14Updated last year
Alternatives and similar repositories for tapa
Users that are interested in tapa are comparing it to the libraries listed below
Sorting:
- An HBM FPGA based SpMV Accelerator☆17Updated last year
- ☆32Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆45Updated 2 weeks ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- ☆20Updated last year
- ☆72Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- ACM TODAES Best Paper Award, 2022☆30Updated 2 years ago
- ☆60Updated 7 months ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆63Updated 4 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25Updated 5 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆23Updated last year
- Processing in Memory Emulation☆22Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆76Updated 6 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆71Updated 7 months ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆72Updated 2 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- RTL generator for SpGEMM☆11Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- NeuraChip Accelerator Simulator☆15Updated last year