UIUC-ChenLab / scalehls

Related projects: ⓘ

• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆192Updated last year
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
  ☆322Updated 4 months ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆212Updated last year
• rapidstream-org / rapidstream-tapa
  RapidStream-TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆149Updated this week
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆131Updated last year
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆118Updated 6 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆102Updated this week
• CMU-SAFARI / ramulator2
  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …
  ☆217Updated 2 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆116Updated last year
• cornell-zhang / allo
  Allo: A Programming Model for Composable Accelerator Design
  ☆122Updated this week
• scalesim-project / scale-sim-v2
  Repository to host and maintain scale-sim-v2 code
  ☆212Updated last week
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆113Updated 4 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
  ☆119Updated last month
• TeCSAR-UNCC / gem5-SALAM
  ☆83Updated 7 months ago
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆115Updated 3 months ago
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆160Updated 4 years ago
• vortexgpgpu / vortex_tutorials
  ☆128Updated 10 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆88Updated 3 weeks ago
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆99Updated last week
• Xilinx / mlir-air
  ☆76Updated this week
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆93Updated 2 months ago
• pnnl / soda-opt
  ☆32Updated 2 months ago
• NVlabs / timeloop
  Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
  ☆321Updated last week
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆62Updated 5 years ago
• accel-sim / accel-sim-framework
  This is the top-level repository for the Accel-Sim framework.
  ☆290Updated 2 weeks ago
• Xilinx / mlir-aie
  An MLIR-based toolchain for AMD AI Engine-enabled devices.
  ☆283Updated this week
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆200Updated last week
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆84Updated 4 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆253Updated last week
• lana555 / dynamatic
  ☆86Updated 6 months ago