A scalable High-Level Synthesis framework on MLIR
☆304May 15, 2024Updated 2 years ago
Alternatives and similar repositories for scalehls
Users that are interested in scalehls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆340Apr 20, 2024Updated 2 years ago
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆69May 9, 2023Updated 3 years ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆413Sep 30, 2026Updated last week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆56Jul 17, 2023Updated 3 years ago
- ☆64Mar 24, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆194Aug 11, 2026Updated last month
- Bridging polyhedral analysis tools to the MLIR framework☆118Sep 9, 2023Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆107Sep 27, 2024Updated 2 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆45Jan 10, 2025Updated last year
- PandA-bambu public repository☆354Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆246Dec 8, 2022Updated 3 years ago
- C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!☆627Jun 19, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A fast, accurate trace-based simulator for High-Level Synthesis.☆78Dec 19, 2025Updated 9 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆74Aug 1, 2025Updated last year
- ☆88Mar 5, 2024Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆134Dec 20, 2022Updated 3 years ago
- Vitis HLS LLVM source code and examples☆417Aug 4, 2026Updated 2 months ago
- PyTorch model to RTL flow for low latency inference☆132Mar 15, 2024Updated 2 years ago
- A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.☆700Updated this week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆175Nov 7, 2023Updated 2 years ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆58Sep 25, 2026Updated 2 weeks ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆206Oct 2, 2026Updated last week
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆35Nov 12, 2024Updated last year
- ☆150Updated this week
- ☆73Feb 16, 2023Updated 3 years ago
- Circuit IR Compilers and Tools☆2,255Updated this week
- EQueue Dialect☆43Feb 3, 2022Updated 4 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆63Mar 17, 2022Updated 4 years ago
- ☆63Aug 4, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- HLS-based Graph Processing Framework on FPGAs☆152Oct 11, 2022Updated 3 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- XLS: Accelerated HW Synthesis☆1,939Updated this week
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆178Mar 12, 2026Updated 6 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆209Nov 14, 2021Updated 4 years ago