A scalable High-Level Synthesis framework on MLIR
☆298May 15, 2024Updated 2 years ago
Alternatives and similar repositories for scalehls
Users that are interested in scalehls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆338Apr 20, 2024Updated 2 years ago
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆69May 9, 2023Updated 3 years ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆393Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆55Jul 17, 2023Updated 3 years ago
- ☆63Mar 24, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆193Mar 8, 2026Updated 4 months ago
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆102Sep 27, 2024Updated last year
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated last year
- A hardware synthesis framework with multi-level paradigm☆45Jan 10, 2025Updated last year
- PandA-bambu public repository☆344Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆243Dec 8, 2022Updated 3 years ago
- C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!☆623Jun 19, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆70Aug 1, 2025Updated 11 months ago
- ☆87Mar 5, 2024Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆77Dec 19, 2025Updated 7 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆129Dec 20, 2022Updated 3 years ago
- Vitis HLS LLVM source code and examples☆412Updated this week
- PyTorch model to RTL flow for low latency inference☆131Mar 15, 2024Updated 2 years ago
- An MLIR-based toolchain for AMD AI Engine-enabled devices.☆667Updated this week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆173Nov 7, 2023Updated 2 years ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆55Jul 10, 2026Updated last week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆198Updated this week
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆34Nov 12, 2024Updated last year
- ☆74Feb 16, 2023Updated 3 years ago
- ☆141Updated this week
- EQueue Dialect☆43Feb 3, 2022Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆38Jan 16, 2025Updated last year
- Circuit IR Compilers and Tools☆2,199Updated this week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆63Mar 17, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆63Aug 4, 2023Updated 2 years ago
- HLS-based Graph Processing Framework on FPGAs☆151Oct 11, 2022Updated 3 years ago
- XLS: Accelerated HW Synthesis☆1,514Updated this week
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆174Mar 12, 2026Updated 4 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆207Nov 14, 2021Updated 4 years ago