Vitis_Accel_Examples
☆604Jun 15, 2026Updated 2 months ago
Alternatives and similar repositories for Vitis_Accel_Examples
Users that are interested in Vitis_Accel_Examples are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vitis In-Depth Tutorials☆1,607Aug 18, 2026Updated last week
- ☆804Jul 13, 2026Updated last month
- Vitis Libraries☆1,123Jun 24, 2026Updated 2 months ago
- Run Time for AIE and FPGA based platforms☆682Updated this week
- ☆120Jul 15, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆387Jan 20, 2025Updated last year
- Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.☆1,801Feb 24, 2026Updated 6 months ago
- VNx: Vitis Network Examples☆164Aug 25, 2025Updated last year
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- SDAccel Examples☆360May 20, 2022Updated 4 years ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆51Jun 17, 2020Updated 6 years ago
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆193Aug 11, 2026Updated 2 weeks ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆343Jan 20, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- HLS-based Graph Processing Framework on FPGAs☆151Oct 11, 2022Updated 3 years ago
- ☆26Dec 1, 2020Updated 5 years ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆906Jan 16, 2026Updated 7 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆120Jun 15, 2025Updated last year
- DPU on PYNQ☆249Aug 12, 2025Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆104Sep 27, 2024Updated last year
- Vitis HLS LLVM source code and examples☆414Aug 4, 2026Updated 3 weeks ago
- AMD OpenNIC Project Overview☆344Dec 20, 2022Updated 3 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆241Apr 23, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AutoSA: Polyhedral-Based Systolic Array Compiler☆243Dec 8, 2022Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Dec 16, 2021Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆95Aug 11, 2026Updated 2 weeks ago
- SDAccel Development Environment Tutorials☆110Apr 8, 2020Updated 6 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆110Jun 30, 2025Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆176Mar 12, 2026Updated 5 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Vitis HLS Library for FINN☆227May 27, 2026Updated 3 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆208Nov 14, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆56Dec 10, 2019Updated 6 years ago
- ☆513Jan 16, 2026Updated 7 months ago
- ☆332Aug 21, 2026Updated last week
- Allo Accelerator Design and Programming Framework (PLDI'24)☆407Updated this week
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆24Apr 27, 2023Updated 3 years ago
- Machine learning on FPGAs using HLS☆2,116Updated this week
- ☆37Apr 10, 2026Updated 4 months ago