Vitis_Accel_Examples
☆584Dec 17, 2025Updated 2 months ago
Alternatives and similar repositories for Vitis_Accel_Examples
Users that are interested in Vitis_Accel_Examples are comparing it to the libraries listed below
Sorting:
- Vitis In-Depth Tutorials☆1,529Jan 29, 2026Updated last month
- ☆762Jan 22, 2026Updated last month
- Vitis Libraries☆1,071Feb 10, 2026Updated 2 weeks ago
- Run Time for AIE and FPGA based platforms☆651Updated this week
- ☆137Nov 26, 2025Updated 3 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- ☆117Jul 15, 2021Updated 4 years ago
- Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.☆1,723Updated this week
- VNx: Vitis Network Examples☆157Aug 25, 2025Updated 6 months ago
- SDAccel Examples☆361May 20, 2022Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆182Aug 16, 2025Updated 6 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆335Jan 20, 2025Updated last year
- Introductory examples for using PYNQ with Alveo☆52Mar 14, 2023Updated 2 years ago
- HLS-based Graph Processing Framework on FPGAs☆149Oct 11, 2022Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Sep 27, 2024Updated last year
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆879Jan 16, 2026Updated last month
- Vitis HLS Library for FINN☆215Updated this week
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Nov 14, 2021Updated 4 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Jul 24, 2024Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆229Apr 23, 2024Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Jul 26, 2024Updated last year
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆116Jun 15, 2025Updated 8 months ago
- ☆24Dec 1, 2020Updated 5 years ago
- Vitis HLS LLVM source code and examples☆403Sep 30, 2025Updated 5 months ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆50Jun 17, 2020Updated 5 years ago
- DPU on PYNQ☆243Aug 12, 2025Updated 6 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆239Dec 8, 2022Updated 3 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆102Jun 30, 2025Updated 8 months ago
- SDAccel Development Environment Tutorials☆109Apr 8, 2020Updated 5 years ago
- AMD OpenNIC Project Overview☆305Dec 20, 2022Updated 3 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆164Updated this week
- ☆499Jan 16, 2026Updated last month
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- ☆315Updated this week
- Machine learning on FPGAs using HLS☆1,812Updated this week
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Dec 16, 2021Updated 4 years ago
- Dataflow compiler for QNN inference on FPGAs☆942Feb 20, 2026Updated last week
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago