Alternatives and similar repositories for HLS_designs

Users that are interested in HLS_designs are comparing it to the libraries listed below

• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆48Updated 7 months ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆86Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆38Updated 4 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• jasonlin316 / Systolic-Array-for-Smith-Waterman
  This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …
  ☆27Updated 6 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆82Updated 6 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• VeriGOOD-ML / public
  ☆63Updated 5 months ago
• sharc-lab / FPGA_ECE8893
  ☆37Updated 6 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆59Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆59Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• hngenc / stellar
  ☆31Updated 11 months ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• suchandler96 / gem5-NVDLA
  ☆35Updated 6 months ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆26Updated last month
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆34Updated 4 months ago
• hyoukjun / OpenSMART
  Public release
  ☆56Updated 6 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆112Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆68Updated 6 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆43Updated 2 weeks ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆31Updated 7 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆126Updated 2 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago