Sibylau / HLS_designs
Systolic array implementations for Cholesky, LU, and QR decomposition
☆42Updated 6 months ago
Alternatives and similar repositories for HLS_designs
Users that are interested in HLS_designs are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆35Updated last month
- view at https://xupsh.github.io/ccc2021/☆23Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆35Updated 4 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- ☆71Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 2 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- ☆70Updated 5 years ago
- ☆35Updated 4 years ago
- ☆23Updated 4 years ago
- DaCH: dataflow cache for high-level synthesis.☆16Updated last year
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- ☆10Updated 2 years ago
- ☆29Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆33Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆34Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆13Updated last year
- ☆46Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆30Updated last month
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆20Updated last year