spcl / apfpLinks
FPGA acceleration of arbitrary precision floating point computations.
☆40Updated 3 years ago
Alternatives and similar repositories for apfp
Users that are interested in apfp are comparing it to the libraries listed below
Sorting:
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated this week
- ☆17Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- ☆12Updated 3 years ago
- ☆30Updated 6 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 8 months ago
- Next generation CGRA generator☆118Updated this week
- ☆36Updated 4 years ago
- Stencil with Optimized Dataflow Architecture☆17Updated last year
- ☆29Updated 8 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 4 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆29Updated 3 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago