spcl / apfpLinks
FPGA acceleration of arbitrary precision floating point computations.
☆40Updated 3 years ago
Alternatives and similar repositories for apfp
Users that are interested in apfp are comparing it to the libraries listed below
Sorting:
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated this week
- DASS HLS Compiler☆29Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆56Updated 3 weeks ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 2 weeks ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- ☆36Updated 4 years ago
- ☆12Updated 3 years ago
- ☆27Updated 4 years ago
- ☆29Updated 8 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- ☆30Updated 6 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago