Serpens is an HBM FPGA accelerator for SpMV
☆23Jul 26, 2024Updated last year
Alternatives and similar repositories for Serpens
Users that are interested in Serpens are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Sep 27, 2024Updated last year
- ☆23Sep 17, 2024Updated last year
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆186Mar 8, 2026Updated 2 weeks ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆49Mar 18, 2026Updated last week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆93Jul 26, 2024Updated last year
- ☆14Feb 14, 2022Updated 4 years ago
- RTL generator for SpGEMM☆10Feb 2, 2021Updated 5 years ago
- A graph linear algebra overlay☆52Apr 26, 2023Updated 2 years ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆15Jun 1, 2025Updated 9 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆75Dec 19, 2022Updated 3 years ago
- ☆16Oct 25, 2022Updated 3 years ago
- NeuraChip Accelerator Simulator☆16Apr 26, 2024Updated last year
- ☆27Feb 27, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆366Mar 13, 2026Updated last week
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆39Mar 30, 2022Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆98Oct 2, 2021Updated 4 years ago
- ☆37Jan 20, 2022Updated 4 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆377Jan 20, 2025Updated last year
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated last year
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Systolic array implementations for Cholesky, LU, and QR decomposition☆49Nov 12, 2024Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- ☆35Dec 22, 2025Updated 3 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- ☆26Nov 4, 2022Updated 3 years ago
- GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks☆36Oct 1, 2023Updated 2 years ago
- A numpy like array programming language optimized with BuildIt☆14Oct 17, 2025Updated 5 months ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆22Aug 8, 2022Updated 3 years ago
- ☆17Feb 13, 2021Updated 5 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- A Generic Distributed Auto-Tuning Infrastructure☆24Jul 29, 2021Updated 4 years ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆19Feb 17, 2022Updated 4 years ago
- Large-scale medical image processing and reconstruction toolbox☆18Feb 13, 2024Updated 2 years ago
- ☆30Apr 26, 2019Updated 6 years ago
- ☆11Oct 28, 2021Updated 4 years ago
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆19Dec 29, 2024Updated last year
- ☆14May 23, 2024Updated last year