Serpens is an HBM FPGA accelerator for SpMV
☆23Jul 26, 2024Updated 2 years ago
Alternatives and similar repositories for Serpens
Users that are interested in Serpens are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆106Sep 27, 2024Updated last year
- ☆24Sep 17, 2024Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated 2 years ago
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆194Aug 11, 2026Updated last month
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆96Aug 11, 2026Updated last month
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆14Feb 14, 2022Updated 4 years ago
- RTL generator for SpGEMM☆13Feb 2, 2021Updated 5 years ago
- NeuraChip Accelerator Simulator☆17Apr 26, 2024Updated 2 years ago
- A graph linear algebra overlay☆52Apr 26, 2023Updated 3 years ago
- Composable HLS library for rapid development of LLM accelerators. FlexLLM enables spatial-temporal hybrid architectures, with parameteriz…☆31Aug 17, 2026Updated last month
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆15Jun 1, 2025Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆82Dec 19, 2022Updated 3 years ago
- ☆16Oct 25, 2022Updated 3 years ago
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆39Mar 30, 2022Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆99Oct 2, 2021Updated 4 years ago
- ☆37Jan 20, 2022Updated 4 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆388Jan 20, 2025Updated last year
- ☆30Feb 27, 2025Updated last year
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated last month
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆24Jul 29, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 4 years ago
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated 2 years ago
- ☆35Dec 22, 2025Updated 9 months ago
- A numpy like array programming language optimized with BuildIt☆14Oct 17, 2025Updated 11 months ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆50Nov 12, 2024Updated last year
- Allo Accelerator Design and Programming Framework (PLDI'24)☆411Updated this week
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- CEMU: Enabling Full-System Emulation of Computational Storage beyond Hardware Limits (ASPLOS'26)☆22Dec 31, 2025Updated 8 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆19Apr 9, 2024Updated 2 years ago
- ☆27Nov 4, 2022Updated 3 years ago
- GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks☆36Oct 1, 2023Updated 2 years ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆35Nov 12, 2024Updated last year
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆21Aug 8, 2022Updated 4 years ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆60Aug 25, 2026Updated 3 weeks ago
- A Generic Distributed Auto-Tuning Infrastructure☆24Jul 29, 2021Updated 5 years ago