UCLA-VAST / SerpensLinks
Serpens is an HBM FPGA accelerator for SpMV
☆19Updated 10 months ago
Alternatives and similar repositories for Serpens
Users that are interested in Serpens are comparing it to the libraries listed below
Sorting:
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- ☆17Updated 9 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- An HBM FPGA based SpMV Accelerator☆13Updated 9 months ago
- ☆41Updated 11 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆55Updated 3 months ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆12Updated 3 weeks ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆81Updated last year
- ☆30Updated 7 months ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆19Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- NeuraChip Accelerator Simulator☆12Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆15Updated 8 months ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆13Updated 4 months ago
- ☆33Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆57Updated 3 months ago
- ☆33Updated 3 weeks ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Updated 4 years ago
- ☆47Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- ☆10Updated 2 years ago
- ☆24Updated 4 years ago