Alternatives and similar repositories for hls_tutorial_examples

Users that are interested in hls_tutorial_examples are comparing it to the libraries listed below

• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆322Updated 6 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆352Updated 6 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆204Updated this week
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆173Updated this week
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆166Updated last year
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆276Updated 3 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆221Updated 2 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆69Updated 6 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆148Updated this week
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆41Updated last year
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆155Updated 2 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆54Updated 6 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆135Updated last month
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆128Updated 5 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆198Updated 5 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆106Updated 7 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆128Updated 5 years ago
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆112Updated last month
• Xtra-Computing / ThunderGP
  HLS-based Graph Processing Framework on FPGAs
  ☆147Updated 2 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆87Updated 2 months ago
• lana555 / dynamatic
  ☆86Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆48Updated last year
• template-hls / template-hls-float
  ☆30Updated 6 years ago