spcl / hls_tutorial_examplesLinks
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
☆199Updated 3 years ago
Alternatives and similar repositories for hls_tutorial_examples
Users that are interested in hls_tutorial_examples are comparing it to the libraries listed below
Sorting:
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆319Updated 4 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆342Updated 4 months ago
- Vitis HLS Library for FINN☆197Updated last week
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆170Updated this week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆143Updated this week
- ☆93Updated 11 months ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆216Updated 6 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆64Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆79Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆110Updated last year
- DPU on PYNQ☆221Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆153Updated 5 years ago
- ☆86Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆184Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated 10 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆269Updated last month
- PyTorch model to RTL flow for low latency inference☆126Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆122Updated 5 years ago
- ☆119Updated 3 years ago