Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
☆205Nov 14, 2021Updated 4 years ago
Alternatives and similar repositories for hls_tutorial_examples
Users that are interested in hls_tutorial_examples are comparing it to the libraries listed below
Sorting:
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆336Jan 20, 2025Updated last year
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- ☆768Jan 22, 2026Updated last month
- ☆47Feb 26, 2026Updated 3 weeks ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆185Mar 8, 2026Updated last week
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33May 30, 2019Updated 6 years ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆881Jan 16, 2026Updated 2 months ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Feb 22, 2021Updated 5 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Sep 23, 2020Updated 5 years ago
- Vitis HLS Library for FINN☆216Feb 25, 2026Updated 3 weeks ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆336Jul 9, 2019Updated 6 years ago
- ☆30Apr 26, 2019Updated 6 years ago
- HLS-based Graph Processing Framework on FPGAs☆149Oct 11, 2022Updated 3 years ago
- Vitis Libraries☆1,077Feb 10, 2026Updated last month
- A scalable High-Level Synthesis framework on MLIR☆291May 15, 2024Updated last year
- FPGA version of Rodinia in HLS C/C++☆42Dec 24, 2020Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆170Nov 7, 2023Updated 2 years ago
- Machine learning on FPGAs using HLS☆1,862Updated this week
- FPGA Accelerator for CNN using Vivado HLS☆338Oct 25, 2021Updated 4 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Jul 24, 2024Updated last year
- Vitis_Accel_Examples☆583Mar 12, 2026Updated last week
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- ☆10Jan 25, 2023Updated 3 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆34Oct 24, 2023Updated 2 years ago
- Vitis In-Depth Tutorials☆1,545Mar 12, 2026Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆93Jul 26, 2024Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Sep 27, 2024Updated last year
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Nov 7, 2019Updated 6 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆284Dec 5, 2019Updated 6 years ago
- Vitis HLS LLVM source code and examples☆406Sep 30, 2025Updated 5 months ago
- ☆47Nov 23, 2023Updated 2 years ago
- A floating-point matrix multiplication implemented in hardware☆32Jan 5, 2021Updated 5 years ago
- ☆244Jun 21, 2022Updated 3 years ago
- AMD University Program HLS tutorial☆124Oct 28, 2024Updated last year