Alternatives and similar repositories for hls_tutorial_examples

Users that are interested in hls_tutorial_examples are comparing it to the libraries listed below

• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆332Updated 10 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆372Updated 10 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆210Updated 2 months ago
• UCLA-VAST / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.
  ☆176Updated 3 months ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆168Updated 2 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆287Updated last month
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆163Updated this week
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆102Updated last year
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆204Updated 5 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆230Updated 3 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆130Updated last year
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆60Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆145Updated 2 weeks ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆69Updated 6 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆234Updated 3 months ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆120Updated last year
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆127Updated 2 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆226Updated 6 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆31Updated 5 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆40Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆108Updated 7 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆54Updated 7 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆97Updated this week
• Xtra-Computing / ThunderGP
  HLS-based Graph Processing Framework on FPGAs
  ☆150Updated 3 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆140Updated 5 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆82Updated 2 years ago