spcl / hls_tutorial_examplesLinks
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
☆204Updated 4 years ago
Alternatives and similar repositories for hls_tutorial_examples
Users that are interested in hls_tutorial_examples are comparing it to the libraries listed below
Sorting:
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆334Updated last year
- Vitis HLS Library for FINN☆214Updated 3 weeks ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆180Updated 5 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆374Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆293Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- HLS-based Graph Processing Framework on FPGAs☆149Updated 3 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 3 weeks ago
- AMD University Program HLS tutorial☆123Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆166Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆226Updated 6 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 7 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Library of approximate arithmetic circuits☆61Updated 3 weeks ago