Licheng-Guo / vivado-hls-broadcast-optimizationView external linksLinks
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
☆32Feb 17, 2021Updated 5 years ago
Alternatives and similar repositories for vivado-hls-broadcast-optimization
Users that are interested in vivado-hls-broadcast-optimization are comparing it to the libraries listed below
Sorting:
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆181Aug 16, 2025Updated 6 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- ☆30Apr 26, 2019Updated 6 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Dec 20, 2022Updated 3 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- DASS HLS Compiler☆29Oct 4, 2023Updated 2 years ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆10Aug 14, 2025Updated 6 months ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆237Dec 8, 2022Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 5 years ago
- Public Release of Stream-Dataflow☆14May 17, 2019Updated 6 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆334Jan 20, 2025Updated last year
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Apr 20, 2024Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆97Jan 29, 2026Updated 2 weeks ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28May 11, 2022Updated 3 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆374Jan 20, 2025Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Sep 27, 2024Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Jul 26, 2024Updated last year
- Stencil with Optimized Dataflow Architecture Compiler☆17May 4, 2020Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- ☆71Mar 22, 2020Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆52Mar 14, 2023Updated 2 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Apr 17, 2016Updated 9 years ago
- Vitis HLS LLVM source code and examples☆403Sep 30, 2025Updated 4 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Nov 14, 2021Updated 4 years ago
- Smith-Waterman Acceleration on Intel’s FPGA with OpenCL for Long DNA Sequences☆18Jan 25, 2019Updated 7 years ago
- FPGA version of Rodinia in HLS C/C++☆40Dec 24, 2020Updated 5 years ago
- ☆87Mar 5, 2024Updated last year
- CNN simd based accelerator using Vitis HLS☆11Jul 15, 2022Updated 3 years ago
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 4 years ago
- Jumpstart your custom DNN accelerator today. This project holds scripts to build and start containers that can compile binaries to the ze…☆10Jun 17, 2020Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆10Jun 1, 2021Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Nov 7, 2023Updated 2 years ago