Alternatives and similar repositories for vivado-hls-broadcast-optimization

Users that are interested in vivado-hls-broadcast-optimization are comparing it to the libraries listed below

• template-hls / template-hls-float
  ☆29Updated 6 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• icgrp / hipr
  ☆15Updated 2 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆45Updated 2 months ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• lana555 / dynamatic
  ☆86Updated last year
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆30Updated 3 weeks ago
• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆14Updated last year
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆20Updated 8 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆36Updated 2 weeks ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• mnnuahg / StamicCGRA
  A static dataflow CGRA with dynamic dataflow execution capability
  ☆10Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆91Updated 8 months ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 2 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆33Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated last year