Alternatives and similar repositories for riscv-v-spec

Users that are interested in riscv-v-spec are comparing it to the libraries listed below

• riscv-software-src / riscv-tests
  ☆1,041Updated last month
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆780Updated this week
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,772Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,915Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,944Updated 2 months ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆648Updated last month
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,171Updated 2 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,144Updated last month
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,291Updated last year
• riscv-non-isa / riscv-arch-test
  ☆578Updated 2 weeks ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆894Updated 4 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,098Updated 2 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,595Updated this week
• riscv-non-isa / rvv-intrinsic-doc
  ☆339Updated last week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆948Updated last month
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆490Updated 2 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆852Updated last month
• vortexgpgpu / vortex
  ☆1,602Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆718Updated 4 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆721Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆885Updated 2 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,066Updated 3 years ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,568Updated this week
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆468Updated 4 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆448Updated this week
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,091Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆718Updated 3 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,052Updated 10 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆586Updated 11 months ago
• riscvarchive / riscv-gcc
  ☆370Updated 2 years ago