riscvarchive / riscv-v-specLinks
Working draft of the proposed RISC-V V vector extension
☆1,045Updated last year
Alternatives and similar repositories for riscv-v-spec
Users that are interested in riscv-v-spec are comparing it to the libraries listed below
Sorting:
- ☆1,053Updated 2 months ago
- RISC-V Opcodes☆791Updated last week
- RISC-V Proxy Kernel☆658Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,959Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,963Updated 4 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- OpenXuantie - OpenC910 Core☆1,311Updated last year
- RISC-V Cores, SoC platforms and SoCs☆896Updated 4 years ago
- Spike, a RISC-V ISA Simulator☆2,813Updated last week
- ☆588Updated 2 weeks ago
- Random instruction generator for RISC-V processor verification☆1,159Updated 3 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,626Updated last week
- ☆1,655Updated this week
- Digital Design with Chisel☆858Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,112Updated 3 months ago
- VeeR EH1 core☆894Updated 2 years ago
- Working Draft of the RISC-V Debug Specification Standard☆494Updated last week
- RISC-V CPU Core (RV32IM)☆1,532Updated 3 years ago
- educational microarchitectures for risc-v isa☆719Updated last week
- ☆344Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆960Updated 2 months ago
- 32-bit Superscalar RISC-V CPU☆1,091Updated 3 years ago
- The RISC-V software tools list, as seen on riscv.org☆470Updated 4 years ago
- The OpenPiton Platform☆729Updated 2 weeks ago
- chisel tutorial exercises and answers☆736Updated 3 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆588Updated last year
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,065Updated last year
- A Linux-capable RISC-V multicore for and by the world☆731Updated 3 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,098Updated 6 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆456Updated last month